A novel majority based imprecise 4:2 compressor with respect to the current and future VLSI industry

Taheri, MohammadReza; Arasteh, Armineh; Mohammadyan, Somaye; Panahi, Atiyeh; Navi, Keivan

doi:10.1016/j.micpro.2019.102962

Cited by 35 publications

(34 citation statements)

References 22 publications

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“…4.15 Design-15 16x16 multiplier with 4:2 compressor in [14] In so many literature 4:2 compressor are used to develop the 8x8 multiplier. The 4:2 compressor as shown in Fig.…”

Section: Design-8 16x16 Multiplier With Scalable Compressormentioning

confidence: 99%

“…In [14] 8x8 multiplier is designed with a 4:2 compressor. The new multiplier is 32x32 width so the usage of any old type compressor increases the design complexity, power and area, so it is easy to design with scalable compressor as shown in Fig.…”

Section: Design-1 32x32 Multiplier With Scalable Compressorsmentioning

confidence: 99%

“…Various multiplier architectures for image processing applications have been done with imprecise compressors proposed in [12] - [14] but the overall errors are limited. The multipliers are constructed with three steps process as follows: (i) dot product generation (ii) reduction of dot product using suitable tree (iii) addition of dot product using adders [15].…”

Section: Introductionmentioning

confidence: 99%

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Prediction of Approximate Multiplier for 16-Bit DICOM Image Contrast Scaling Using Classical Machine Learning Approach

dominic

Deepa

2021

Preprint

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The role of approximate arithmetic are involved when the processors are used for multimedia signal processing application. The impact of multiplier is very important in many processes done by these processors. The compressors are the core architecture for reduction stage if the multiplier width is increased. Later approximations are done in the compressor to limited error without affecting the signal standard. The design of scalable-split compressor is designed in this work and a counter matching method has been developed for approximation. The design of 32x32 and 16x16 multiplier with these new compressors are synthesised in 45nm Synopsis Design Compiler and shows an improvement of 25 % of Chip area and 27% power. The split-scalable architecture attempts to reduce the delay with trade-off in area and power. Mean Error Distance (MED) and Normalized Error Distance (NED) are the parameters that ensure the quality of any approximate arithmetic based design. 16-bit medical images are processed with both existing and proposed multipliers then the Peak Signal to Noise Ratio (PSNR) is compared. Finally with several input nature and targeted PSNR the best system is identified using classical machine learning model.

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“…4.15 Design-15 16x16 multiplier with 4:2 compressor in [14] In so many literature 4:2 compressor are used to develop the 8x8 multiplier. The 4:2 compressor as shown in Fig.…”

Section: Design-8 16x16 Multiplier With Scalable Compressormentioning

confidence: 99%

Section: Design-1 32x32 Multiplier With Scalable Compressorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Prediction of Approximate Multiplier for 16-Bit DICOM Image Contrast Scaling Using Classical Machine Learning Approach

dominic

Deepa

2021

Preprint

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“…A majority gate is a voter circuit, which votes to majority inputs. Inputs are always odd numbers and greater than one [11]. The AND gate and the OR gate are designed with the MAJ.…”

Section: Qca Backgroundmentioning

confidence: 99%

A New Bio Inspired Majority Device MAJ (A, B, C)

Kandelous¹,

Moosavi²,

Daliri³

et al. 2019

jncog

Self Cite

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In this article, we try to model the effect of the changes of the threshold voltage of two positive inputs to negative ones using nanotechnology-based on Quantum Dot Cellular automata (QCA). In order to do so, the voter of a Majority cell has been modified resulting in amplifying the negative effect of the upper and the lower cells. Besides this Brain-inspired approach can be used to design a very fast Majority function with two negative inputs based on QCA.

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“…It consumes the most power, and causes the highest delay of all the above-mentioned stages, many research works are still done on reducing these parameters for designing a high speed multiplier. Rather than adders, compressors can be used to improve the circuit's regularity, lowering latency and power consumption during the partial product reduction stage [3]. Approximate compression is very crucial while dealing with low-power circuits.…”

Section: Introductionmentioning

confidence: 99%

Design of High speed Multiplier using Input Scrambled 5-3 compressor for Error Tolerant image processing

Savio¹,

Deepa²,

Dharshini³

et al. 2022

J. Phys.: Conf. Ser.

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The imprecise multiplier has received a lot of attention for many high-performance systems used today such as in Image Processing, Microprocessors where multiplication is one of the fundamental operations. In order to shorten the reduction stages of imprecise multiplier which is essential for reducing the critical path delay, complexity and power consumption, higher compressor adders are employed. In this paper, a novel comparison technique for approximation is implemented using a 5:3 compressor which is area, power, and delay efficient. This compressor is used for developing an 8x8 multiplier. Then the proposed 8x8 multiplier and the existing multiplies are compared for various factors including the evaluation analysis of error rate (ER) and normalised error distance (NED). When compared to existing designs, the proposed 5:3 compressor has a better delay of 18%. After image multiplication, the recommended multiplier is utilised to compare PSNR.

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A novel majority based imprecise 4:2 compressor with respect to the current and future VLSI industry

Cited by 35 publications

References 22 publications

Prediction of Approximate Multiplier for 16-Bit DICOM Image Contrast Scaling Using Classical Machine Learning Approach

Prediction of Approximate Multiplier for 16-Bit DICOM Image Contrast Scaling Using Classical Machine Learning Approach

A New Bio Inspired Majority Device MAJ (A, B, C)

Design of High speed Multiplier using Input Scrambled 5-3 compressor for Error Tolerant image processing

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