A novel memory cell using flash array contactless EPROM (FACE) technology

Abstract

A new single transistor Flash memory cell which utilizes channel hot electron injection for programming and Fowler-Nordheim tunneling for erase is described. This Flash memory technology employs a "buried" N+ bitline to connect the memory transistors rather than metal and contacts. Elimination of contacts results in a 45% cell area shrink of the conventional ETOX" cell (based on 1.0 pm design rules). A 4.48 pm2 cell area is also realized by using a 0.8 pm technology. In addition to this tremendous cell scalability, the diffusion comer induced erase threshold "bimodality" can be reduced due to the intrinsic stripe geometries in the memory array. Furthermore, the ContacVMetal related layout rules can be relaxed which allows this contactless approach to be extended to future generations without requiring complicated contact processing. Hence, the Flash Array Contactless EPROM (FACE) technology lends itself to a very compact cell as well as a more manufacturable process.

Influence of source coupling on the programming and degradation mechanisms of split-gate flash memory devices

“…The channel-hot-electron injection (CHEI) mechanism has been widely used as a programming technique for nonvolatile memory application in the past [1]. However, owing to the lower programming efficiency, devices utilizing the CHEI mechanism for programming usually need an external high-voltage power supply in order to program the cells within a reasonable time [2][3][4]. Basically, this is due to an inherent incompatibility of having a high hot-carrier generation rate and having an oxide field favourable for electron injection [5][6][7].…”