A Novel Modular Positive-Sequence Synchrophasor Estimation Algorithm for PMUs

Messina, Francisco; Marchi, Pablo; Vega, Leonardo Rey; Galarza, Cecilia G.; Laiz, H.

doi:10.1109/tim.2016.2637578

Cited by 40 publications

(26 citation statements)

References 24 publications

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“…Usman [4] shows a version of IEC/IEEE Std Figure D.1 but does not discuss the filters. Messina [21] uses a phase locked loop (PLL) to change the local oscillator (LO) frequency to track the mains frequency and thus remove any accuracy degradation caused by the mains frequency and the LO frequency being different.…”

Section: Related Workmentioning

confidence: 99%

A Phasor Measurement Unit Algorithm Using IIR Filters for FPGA Implementation

Kikkert

2019

Electronics

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Phasor measurement units (PMU) are increasingly used in electrical power transmission networks, to maintain stability and protect the network. PMUs accurately measure voltage, phase, frequency, and rate of change of frequency (ROCOF). For reliability, it is desirable to implement a PMU using an FPGA. This paper describes a novel algorithm, suited to implementation in an FPGA and based on a simple PMU block diagram. A description of its realization using low hardware complexity infinite impulse response (IIR) filters is given. The IEC/IEEE standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power systems, describes "reference" Finite Impulse Response (FIR) filters for implementing PMU hardware. At the 10 kHz sampling frequency used for our implementation, each "reference" FIR filter requires 100 multipliers, while an 8th order IIR filter only requires 12 multipliers. This paper compares the performance of different order IIR filter-based PMUs with the performance of the same PMU algorithm using the IEC/IEEE FIR reference filter. The IIR-based PMU easily satisfies all the requirements of IEC/IEEE standard and has a much better out of band signal rejection performance than a FIR-based PMU. Steady state errors for a rated voltage ± 10% and a rated frequency ± 5 Hz are < 0.000001% for total vector error (TVE) and < 1 µHz for frequency, with a latency of two mains cycles.

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Section: Related Workmentioning

confidence: 99%

A Phasor Measurement Unit Algorithm Using IIR Filters for FPGA Implementation

Kikkert

2019

Electronics

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“…Luego, los filtros 10 Esta correspondencia tiene sentido pues generalmente se utilizan ventanas positivas, es decir, tales que wn > 0 para todo n ∈ N . 11 La misma puede hallarse fácilmente mediante el método de multiplicadores de Lagrange.…”

Section: Métodos Basados En El Diseño De Filtrosunclassified

Estimación de Sincrofasores en Redes Eléctricas Inteligentes: de Modelos a Restricciones de Diseño

Messina

Vega

Galarza³

2017

Elek.

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Presentamos en primer lugar una reseña de dos populares clases de métodos de estimación de sincrofasores. Ellas son la clase de métodos basados en la transformada de Fourier discreta (DFT) y la transformada de Taylor-Fourier (TFT), que surgen de un modelo de fasor constante y polinómico, respectivamente. Se exponen las limitaciones de estos métodos, que surgen por los propios modelos asumidos, lo cual los hace poco apropiados en situaciones donde el fasor no puede representarse en términos tan simples. Este problema puede resolverse con los estimadores basados en optimización convexa semi-infinita (CSIP), un enfoque novedoso que también es descripto. En particular, enfatizamos las restricciones asociadas con las situaciones más críticas para los métodos basados en modelos, mostrando cómo controlar precisamente el desempeño de los estimadores en dichos casos. Finalmente, mostramos que los estimadores DFT y TFT son instancias particulares del estimador CSIP, de modo existe una conexión entre estos dos enfoques aparentemente diferentes. Esto abre la puerta para futuros análisis y desarrollos.

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“…The discrete Fourier transform (DFT) has been widely used as phasor estimator due to its simplicity; regrettably, its poor performance under dynamic conditions [6], [7] compromises the compliance with the standard, leading to the development of new DFT-based algorithms. The interpolated DFT (IpDFT) has been tested for P class and M class PMUs [8], [9].…”

Section: Introductionmentioning

confidence: 99%

A New Phasor Estimator for PMU Applications: P Class and M Class

Razo-Hernández

Mejia-Barron

Granados-Lieberman

et al. 2020

Journal of Modern Power Systems and Clean Energy

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Phasor measurement units (PMUs) are fundamental tools in the applications of modern power systems, where synchronized phasor estimations are needed. The accuracy and dynamic performance requirements for phasor, frequency, and rate of change of frequency (ROCOF) estimations are established in the IEEE Std. C37.118.1-2011 along with the IEEE Std. C37.118.1a-2014, where two PMU performances are suggested: P class filters for applications requiring fast response and M class filters for applications requiring high rejection to aliased signals. In this paper, a methodology to design new phasor estimators that satisfy the P class and M class requirements in PMUs is presented. The proposed methodology is based on finite impulse response filters, brick-wall filters, and complex filter design concepts, where frequency range, time performance, harmonic rejection and out-of-band interference requirements are considered in its design. A comparative analysis using the reference model given by the IEEE Std. C37.118.1 is presented. The results show the effectiveness of the phasor estimators under steady-state and dynamic conditions according to the PMU standard, making them suitable tools for applications in power systems.

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A Novel Modular Positive-Sequence Synchrophasor Estimation Algorithm for PMUs

Cited by 40 publications

References 24 publications

A Phasor Measurement Unit Algorithm Using IIR Filters for FPGA Implementation

A Phasor Measurement Unit Algorithm Using IIR Filters for FPGA Implementation

Estimación de Sincrofasores en Redes Eléctricas Inteligentes: de Modelos a Restricciones de Diseño

A New Phasor Estimator for PMU Applications: P Class and M Class

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