A Novel Multiplexer-Based Low-Power Full Adder

Jiang, Yingtao; Al-Sheraidah, A.; Wang, Yuke; Sha, Edwin Hsing-Mean; Chung, Jin-Gyun

doi:10.1109/tcsii.2004.831429

Cited by 159 publications

(62 citation statements)

References 4 publications

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“…Low-power multiplexer-based 1-bit full adder that uses only 12 transistors and the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder. Also, it consumes 23% less power than another 10-transistor adder and is 64% faster [3]. Low power operations [4], which can use the lowest possible supply voltage coupled with architectural, logic style, circuit and technology optimizations.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Reversible Control and Full Adder Unit Using HNG Reversible Logic Gate

Agrawal¹

2017

IJRASET

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Reversible logic is one of the most vital subject at present time,used to reduce the power dissipation that occurs in conventinal circuits by preventing the loss of information, in this paper we are presenting the implementation of efficient arithmetic logic i.e. reversible control unit and reversible full adder unit, using reversible HNG logic gates which can performseven logical operations and eight arithmetic operations. Alsoour focus on improving the performance parameters of design: number of constant inputs, number of garbage outputs, quantum cost, number of gates and propagation delay compared to existed designs.

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Section: Introductionmentioning

confidence: 99%

Implementation of Reversible Control and Full Adder Unit Using HNG Reversible Logic Gate

Agrawal¹

2017

IJRASET

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“…These are useful for low power and high-speed circuits in [12]. A new 16 transistor full adder design reported in [13] using flexible design method the basic design of the whole full adder it is realized by two six transistors XNOR and one 2:1 multiplexer. This high-speed design can provide the output, with proper voltage swing for the low supply voltage.…”

Section: Introductionmentioning

confidence: 99%

Low-Power High-Speed Double Gate 1-bit Full Adder Cell

Kumar¹,

Roy²,

Bhunia³

2016

International Journal of Electronics and Telecommunications

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Abstract-In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94µW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.Keywords-Low-power full-adder, Low-power CMOS design, multiplexer based full-adder design, multi-threshold voltage based Full-adder design, pass transmission logic.

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“…So as a whole the full adder performance affects the system performance. A wide variety of full adders form the conventional to hybrid and in different logic styles have been reported in the literature [1]- [12].…”

Section: Introductionmentioning

confidence: 99%

“…The adders that are considered for this work include the conventional CMOS full adder [1], 16T full adder [2], 14T FA [3], 10T FA [4], 8T FA [5], mirror adder [6], multiplexer based adder [7], transmission based adder [8], conventional D3L [9], sp-D3L all three versions as in ( [10], [12]), BBL-PT full adder [11]. The Ripple carry adders (RCA) of different sizes like 8-bit, 16-bit, 32-bit are designed with the above full adders.…”

Section: Introductionmentioning

confidence: 99%