A novel particle swarm optimization approach for VLSI routing

Khan, Abhinandan; Laha, Sulagna; Sarkar, Subir Kumar

doi:10.1109/iadcc.2013.6514231

Cited by 14 publications

(6 citation statements)

References 5 publications

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“…Routing, both global and local, has a significant impact on the entire chip performance and efficient routing algorithms (with further modifications leading to improved performance) [8] are obviously the key to success in the future in the domain of VLSI physical design. In this work, our main objective has been to obtain the minimum possible wire length with the help of a global routing algorithm.…”

Section: Discussionmentioning

confidence: 99%

A Global Routing Optimization Scheme Based on ABC Algorithm

Bhattacharya

Khan

Sarkar

2014

Smart Innovation, Systems and Technologies

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Abstract. Rapid technological advancements are leading to a continuous reduction of integrated chip sizes. An additional steady increase in the chip density is resulting in device performance improvements as well as severely complicating the fabrication process. The interconnection of all the components on a chip, known as routing, is done in two phases: global routing and detail routing. These phases impact chip performance significantly and hence researched extensively today. This paper deals with the global routing phase which is essentially a case of finding a Minimal Rectilinear Steiner Tree (MRST) by joining all the terminal nodes, known to be an NP-hard problem. There are several algorithms which return near optimal results. Recently algorithms based on Evolutionary Algorithms (such as Genetic Algorithm) and based on Swarm Intelligence (such as PSO, ACO, ABC, etc.) are being increasingly used in the domain of global routing optimization of VLSI Design. Swarm based algorithms are an emerging area in the field of optimization and this paper presents a swarm intelligence algorithm, Artificial Bee Colony(ABC) for solving the routing optimization problem. The proposed algorithm shows noteworthy improvements in reduction of the total interconnect length. The performance of this algorithm has been compared with FLUTE (Fast Look Up Table Estimation) that uses Look Up Table to handle nets with degree up to 9 and net breaking technique for nets with degree up to 100. It is used for VLSI applications in which most of the nets have a degree 30 or less than that.

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Section: Discussionmentioning

confidence: 99%

A Global Routing Optimization Scheme Based on ABC Algorithm

Bhattacharya

Khan

Sarkar

2014

Smart Innovation, Systems and Technologies

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“…Even though this paradigm can be applied to very different problems, the main applications are in robotics [Kube 1997;Sahin et al 2002;Ducatelle et al 2011;Brambilla et al 2013], up to the most recent achievements with large swarms of more than 1,000 robots [Rubenstein et al 2014]. Other interesting application fields are communication networks [Schoonderwoerd et al 1996;Di Caro et al 2004;Zhang et al 2014] and optimization metaheuristics [Dorigo and Stützle 2004;Kennedy et al 2001] (even applied to integrated architectures but only to solve problems such as partitioning [Kuntz and Layzell 1997], placement [Rout et al 2010], and routing [Khan et al 2013] at design time). The interested reader can find several application fields in Bonabeau et al [1999].…”

Section: Rationalementioning

confidence: 99%

Computing Swarms for Self-Adaptiveness and Self-Organization in Floating-Point Array Processing

Pani

Palumbo

et al. 2015

ACM Trans. Auton. Adapt. Syst.

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Advancements in CMOS technology enable the integration of a huge number of resources on the same systemon-chip. Managing the consequent growing complexity, including fault tolerance issues in deep submicron technologies, is a hard challenge for hardware designers. Self-organization may represent a viable path toward the development of massively parallel architectures in current and future technologies. This approach is progressively more studied in multiprocessor architectures where, however, a further mind-set shift in terms of programming paradigm is required. In this article, self-organization and self-adaptiveness are exploited for the design of a coprocessing unit for array computations, supporting floating-point arithmetic. From the experience of previous explorations, an architecture embodying some principle of swarm intelligence to pursue adaptability, scalability, and fault tolerance is proposed. The architecture realizes a loosely structured collection of hardware agents implementing fixed behavioral rules aimed at the best exploitation of the available resources in whatever kind of context without any hardware reconfiguration. Comparisons with off-the-shelf very long instruction word (VLIW) digital signal processors (DSPs) on specific tasks reveal similar performance thus not paying the improved robustness with performance. The multitasking capabilities, together with the intrinsic scalability, make this approach valuable for future extensions as well, especially in the field of neuronal networks simulators.

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“…Dong et al [6] proposed a routing algorithm based on improved Discrete PSO in which a novel encoding for DPSO and update functions are performed to find the RSMT. The results of these methods [6][7][8] were compared with conventional methods and proved to give a better routing optimization.…”

Section: Related Workmentioning

confidence: 99%

“…A heuristic approach to find the optimal routing path and buffer location simultaneously for minimal interconnect delay was presented in [8] and in [7], Prim's Algorithm was modified and implemented as a principle of finding the cost of the RSMT. Dong et al [6] proposed a routing algorithm based on improved Discrete PSO in which a novel encoding for DPSO and update functions are performed to find the RSMT.…”

Section: Related Workmentioning

confidence: 99%

“…Then, an algorithm for multi-channel routing was considered and compared with 'Chameleon', which is another multi-channel routing algorithm in the twolayer VH and three-layer HVH routing models. Particle swarm optimization (PSO) has been proposed in various works [6][7][8] for VLSI routing. These techniques find the minimum cost of Rectilinear Steiner Minimal Tree (RSMT), which is a NP-problem.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Performance Analysis of Shared Buffer Router Architecture for Low Power Applications

Deivakani¹,

Shanthi²

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

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A novel particle swarm optimization approach for VLSI routing

Cited by 14 publications

References 5 publications

A Global Routing Optimization Scheme Based on ABC Algorithm

A Global Routing Optimization Scheme Based on ABC Algorithm

Computing Swarms for Self-Adaptiveness and Self-Organization in Floating-Point Array Processing

Performance Analysis of Shared Buffer Router Architecture for Low Power Applications

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