A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

Abstract

Abstract-The main problem in extending continuous-time filtering to higher frequencies is the sensitivity of high-frequency filters to analog integrator nonidealities such as finite dc gain and parasitic poles. The use of a cascode stage introduces internal nodes, and hence a nondominant pole, in the signal path. This has been overcome using a novel phase compensation scheme which does not require tuning of the compensating element, and is itself unaffected by tuning of the integrator's unity-gain frequency or quality factor. The scheme is based upon a MOS version of the "multi-tanh principle" where the linear range of a transconductor is divided between at least two unbalanced differential pairs operating in parallel. The common-source node of an unbalanced differential pair is not ac ground and the associated pole-zero pair may be harnessed to cancel the parasitic pole introduced by the cascode stage. The feasibility of the proposed design was evaluated with the fabrication of a test-chip on a 0.25 m 2.5 V standard digital CMOS process. Measurements confirm that the group delay response is flat ( 2%) over a five octave frequency range (3.5-112 MHz or 0.058-1.87 ).

A 6^th order continuous time band-pass Sigma Delta Analog to Digital modulator with active inductor based resonators

“…In order to obtain greater linearity a multi-tanh version of the NIC circuit is used. This requires the addition of two extra cross-coupled pairs of MOSFETs with a 2:1 size ratio [5] [6]. When the signal is large and the symmetrical differential pair has saturated, the unbalanced differential pairs can still provide a differential current proportional to the input voltage.…”

Analysis and Experimental Validation of Large-Signal Linearization for Low-Power Complex OTA-C Filters

“…Furthermore, bulk degeneration resistors in differential pairs can be utilized to improve linearity [15]. On the other hand, a linearity enhancement technique with three unbalanced differential pairs has been introduced in [16]. In this paper, a power-efficient linearization method is analyzed and experimentally validated, which distinguishes itself from previous works by combining three elements: unbalanced operation with only two unbalanced pairs, a new adaptive biasing circuit, and resistive degeneration.…”

Obtaining maximally flat transconductances with any number of multiple coupled differential pairs

“…As the obtained linear range is very small, it is used, for instance, in current steering DACs [1] but, in order to work as a transconductor, a higher linear range is desirable. In the last years, a multitude of new techniques that manage to increase significantly this linear range has been developed: multiple coupled differential pairs [2][3][4][5][6][7][8][9][10][11][12][13], bulk as an active terminal [3], back-gate offset voltages [4,14], source degeneration via diode connected transistors [5,6], source degeneration via diffusors [5,7,8,15,16], source degeneration via resistors [17] and others [18][19][20][21]. The use of multiple coupled differential pairs is probably the most elegant solution as it is suited for low supply voltage, it is completely compatible with many other designing techniques and allows the customization of the shape of its transconductance.…”