A Novel Propagation Model for Heavy-Ions Induced Single Event Transients on 65nm Flash-based FPGAs

Du, Boyang; Colucci, M.; Aranci, L.; Artina, E.; Ratti, N.; Picardi, E.; Mancini, R.; Piloni, V.; Azimi, Sarah; Sterpone, Luca

doi:10.1109/radecs50773.2020.9857686

Cited by 2 publications

(1 citation statement)

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“…The Single Event Transient analysis has been performed on the entire mapped circuitry on the radiation-hardened FPGA, therefore transient pulses have been injected and propagated on the resources belonging to the ZFNet architecture, on the synchronized weight buffer and on the Input/Output DMAs. For the purpose of our analysis, we used a drift-based transient pulse voltage glitch model introduced in [22] and developed an analyzer tool for FPGAs in [23] adapted to the radiationhardened 65-nm Flash-based FPGA technology. We modeled four different SET pulses in order to mimic the overall scenario of radiation-induced SET pulses thus analyzing pulses with the following widths: 150 ps, 250 ps, 350 ps, and 450 ps.…”

Section: B Single Event Transient Analysismentioning

confidence: 99%

CNN-Oriented Placement Algorithm for High-Performance Accelerators on Rad-Hard FPGAs

Sterpone,

Azimi,

Sio

2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Convolutional Neural Networks (CNNs) are quickly becoming one of the most common applications running on hardware accelerators. Considering Field Programmable Gate Arrays (FPGAs), due to their high flexibility and computational performance, they are suitable for fast classification tasks and therefore, pave the way for new machine learning inference approaches. In this work, we first designed a fully interconnected CNN architecture implementable on a single FPGA. Secondly, we developed a new Neural Node-oriented placement algorithm to enable resilient CNN accelerators on space-grade FPGAs. The proposed solution reduces the single event transient error sensitivity of CNN single neuron cores while achieving high performance and effective overall convolutional architecture fault tolerance. The developed approach has been applied and integrated into a state-of-the-art Radiation Tolerant FPGAs (RTG4) implementation flow. The experimental evaluation has been performed on a Microchip test board through benchmark application performance evaluation and transient error analysis. Experimental results demonstrate an improvement of 27.2% of the maximal working frequency and a reduction of the transient error sensitivity of about three times with respect to the previous mitigation approaches.

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Section: B Single Event Transient Analysismentioning

confidence: 99%