A Novel Pulse Position Modulator for Compressive Data Acquisition

Abstract

This work extends the development of the nonuniform Parallel Digital Ramp Pulse Position Modulation Analog-to-Digital Converter (PDR-ADC) architecture. The continuous to discrete transform of the PDR-ADC is achieved by partitioning the signal amplitude axis into P nonoverlapping partitions that sample the analog input at input signal driven instances. Each partition contains L uniform levels with different quantization step sizes such that the dynamic range of the partitions are related as a geometric series. It is shown that this new architecture satisfies the Nyquist requirement on average (Beutler's condition) and results in a random additive sampling architecture that is alias free (Shapiro-Silverman condition). Additionally, it is shown that the geometric partitioning causes the signal-to-quantization noise ratio (SQNR) to remain approximately constant. A comprehensive design paradigm is presented, including circuits to affect the desired response, the format of the encoded digital samples and the corresponding transformation to determine the equivalent analog voltage. Lastly, although the thrust of this paper is not reconstruction techniques, reconstruction is, nevertheless, compulsory, and recovery and reconstruction is demonstrated through simulations.

Signal-to-Quantization Noise Ratio of the Parallel Digital Ramp Analog-to-Digital Converter

“…Conceptually, the PDR-ADC may initially be regarded as a parallel arrangement of uniform quantizers as shown in Figure 2. Each quantizer, in Figure 2, is referenced independently and spans a different range of possible input signal values, thus partitioning the input signal axis [19,15]. In such an arrangement, if P is the number of partitions, and if each quantizer contains the same number of quantization levels, L, where L = 2 N , and if each quantizer has a dynamic range, V re f P , so that together the P partitions span V re f , then the quantization step size is given by:…”

“…The PDR-ADC, however, operates from a single N bit digital counter, that generates 2 N counts, that are scaled and shifted to generate the required number of partitions [15]. Consequently, if a single digital ramp ADC, operating with clock rate, T CLK , were required to span the same dynamic range, V re f , this single digital ramp would take P • 2 N • T CLK seconds.…”

“…Of the various methods described, the nonuniform Level Crossing (LC) architectures appear to dominate the recent literature, [9] - [14]. In [15], the PDR-ADC was introduced and circuits to affect the desired response developed. A specific partitioning scheme based upon partitioning the signal amplitude axis as a geometric series was developed in terms of circuit parameters.…”

“…Lastly, the encoder, E, converts the quantizer output into the corresponding digital word. Let the number of bits in the digital word be, N, and let, V re f , be the analog reference voltage for the ADC, then, as is well known, that the quantization step size, ∆ is [15,16]:…”