A Novel QCA based Compact Scan Flip-flop for Digital Design Testing

Abstract

Quantum-dot Cellular Automata (QCA) is an emerging technology used for computation at nano scale. It is an excellent alternative for the conventional CMOS technology. QCA provides us with low energy, high speed, faster switching speed and compact structures for logical circuits. Testing is the integral part of the design verification, scan flip-flop is used for device testing. It is used in processors for a built-in self-test. The objective of this paper is to design an optimized structure of a scan flip-flop which occupies less area and dissipates minimum energy compared to the previously designed architectures. The efficiency of the proposed structure is analyzed in terms of cell count, energy dissipation, and area occupied by the logical circuit. Proposed scan flip flop has a cell count of 32 and an energy dissipation of 0.0105 eV which is 20 % more efficient in terms of cell count and 29 % more efficient than the previous designs. The CAD tool, QCADesigner is used for design and simulation. Cells have a dimension of 18 nm in height and 18 nm in breadth and there is a distance of 2 nm between these cells. Bi-stable and coherence vector simulation engines are used in the tool for simulation.

Area and energy optimized Hamming encoder and decoder for nano-communication

“…Clocks are required in all QCA cells to control and synchronize the information flow. QCA has four clock phases [2].…”

“…The technology comprises a QCA cell, a majority voter (MV) gate, an inverter, a simulation engine setup, and a simulation-type setup. For developing digital logic circuits with a high level of integration, switching speed, and lower energy dissipation, QCA is preferred [1][2][3].…”