2008 International Symposium on Telecommunications 2008
DOI: 10.1109/istel.2008.4651389
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A novel QCA multiplexer design

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Cited by 49 publications
(26 citation statements)
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“…They have also shown a 4:1 MUX which consists of 215 cells covering an area of inputs is 6 clock phases i.e. 1.5 clock cycles.In [4] Hashemi et al have proposed multiplexer in three layers in which the first layer is the backbone of the circuit. This new design is denser with four clocks latency and faster.…”
Section: Previous Workmentioning
confidence: 99%
“…They have also shown a 4:1 MUX which consists of 215 cells covering an area of inputs is 6 clock phases i.e. 1.5 clock cycles.In [4] Hashemi et al have proposed multiplexer in three layers in which the first layer is the backbone of the circuit. This new design is denser with four clocks latency and faster.…”
Section: Previous Workmentioning
confidence: 99%
“…Thus the number of inputs and outputs in reversible gates are equal. Any arithmetic logic unit [6] must be able to produce a variety of logic outputs based on inputs determined by the programmer for implementation in an instruction set architecture. Therefore, reversible logic devices used in an environment must have both fixed select input lines that receive op-code signals manipulated by the programmer and permanent output lines where the result of the logical output is produced [3].…”
Section: Reversible Logic Gatesmentioning
confidence: 99%
“…In article [18], a new design has been proposed. In this design 31 number of cell have been used and four clocks are applied there, so total delay is 360 0 .…”
Section: Earlier Workmentioning
confidence: 99%
“…Recent methodologies [15,16,17,18] have shown a lot of improvements in designing QCA multiplexers in terms of complexities (number of cells), areas and speed(delay) over their past methodologies. But the proposed one is having less complexity, consume less area and higher speed as compared to recent methodologies.…”
Section: Analysis Of Proposed Designmentioning
confidence: 99%