A Novel Refreshment Circuit for 2T1M Neuromorphic Synapse

Abstract

Neuromorphic systems are the future computing systems to overcome the von Neumann’s power consumption and latency wall between memory and processing units. The two main components of any neuromorphic computing system are neurons and synapses. Synapses carry the weight of the system to be multiplied by the neuromorphic attributes, which represent the features of the task to be solved. Memristor (memoryresistor) is the most suitable circuit element to act as a synapse. Its ability to store, update and do matrix multiplication in nanoscale die area makes it very useful in neuromorphic synapses. One of the most popular memristor synapse configurations is the two-transistor–one-memristor (2T1M) synapse. This configuration is very useful in neuromorphic synapses for its ability to control reading and updating the weight on a chip by signals. The main problem with this synapse is that the reading operation is destructive, which results in changing the stored weight value. In this paper, a novel refreshment circuit is proposed to restore the correct weight in case of any destructive reading operations. The circuit makes a small interrupt time during operation without disconnecting the memristor, which makes the circuit very practical. The circuit has been simulated by using hardware-calibrated CMOS TSMC 130[Formula: see text]nm technology on Cadence Virtuoso and linear ion drift memristor Verilog-A model. The proposed circuit achieves the refreshment task accurately for several error types. It is used to refresh 2T1M synapse with any destructive reading signal shape.