A Novel Routing Algorithm for On-Chip Communication in NoC on Diametrical 2D Mesh Interconnection Architecture

Ghosal, Prasun; Das, Tuhin Subhra

doi:10.1007/978-3-642-31600-5_65

Cited by 10 publications

(5 citation statements)

References 7 publications

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“…The information bundle comprises the data of the source and goal arrange. [23][24][25] The MSwitch peruses the location of the goal and course in the specific heading. The NoC MSwitch forms the fixed length information through the handling components.…”

Section: Literaturementioning

confidence: 99%

Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine Learning

2021

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Network on chips (NoCs) 3D design expansion is continuously changing to produce energy-efficient NoCs. In this production, the major requirement is to have continuous monitoring with great effort of engineering process and policies which tries to incorporate the machine learning techniques for producing EE-NoCs (energy-efficient NoCs). The learning is a method of neural network system. This thought process of machine learning art in producing EE-NoCs resulted in better production. The internal architecture framed is Power Gate Deployment, voltage instant changeovers, and scaling in the frequenting simultaneous reduction in power. Multiprocessor architecture and platform have been introduced to extend the applicability of Moore's law. The solution for the multiprocessor system architecture is application-specific NoC architecture which are emerging as a leading technology. NoC can be useful in addressing many requirements such as inter-process communication, bandwidth, deadlock avoidance and routing structure. With power now the first order design constraint early stage estimation of NoC power, performance, and area has become important. The topology, switching and routing techniques are necessary in the NoC architecture design. This paper focuses on the n-dimension hypercube network on chip topological structure. It is used for more efficient performance and reliability for data communication. Therefore, in this paper, we are going to go through a bunch of different concepts, such as routing deadlock, and the router pipeline. Keywords Network on chip (NoC) • Power gate • Machine learning • Frequency scale • System on chip (SOC)This article is part of the topical collection "Computational Statistics" guest edited by Anish Gupta, Mike Hinchey, Vincenzo Puri, Zeev Zalevsky and Wan Abdul Rahim.

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Section: Literaturementioning

confidence: 99%

Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine Learning

2021

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“…Some studies suggest ways to improve known regular topologies by implementing additional long irregular links to reduce the diameter of the topology. In [24] it is proposed to extend the mesh topology by 8 regular connections. The number of additional connections does not change with the increase in dimensionality of the topology; however, it makes it possible to halve the diameter.…”

Section: Improved Non-regular Mesh-like Noc Topologiesmentioning

confidence: 99%

Development of routing algorithms in networks-on-chip based on ring circulant topologies

Romanov

2019

Heliyon

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This work is devoted to the study of communication subsystem of networks-on-chip (NoCs) development with an emphasis on their topologies. The main characteristics of NoC topologies and the routing problem in NoCs with various topologies are considered. It is proposed to use two-dimensional circulant topologies for NoC design, since they have significantly better characteristics than most common mesh and torus topologies, and, in contrast to many other approaches to improving topologies, have a regular structure. The emphasis is on using ring circulants which although in some cases have somewhat worse characteristics than the optimal circulants, compensate by one-length first generatrix in such graphs that greatly facilitate routing in them. The paper considers three different approaches to routing in NoCs with ring circulant topology: Table routing, Clockwise routing, and Adaptive routing. The algorithms of routing are proposed, the results of synthesis of routers, based on them, are presented, and the cost of chip resources for the implementation of such communication subsystems in NoCs is estimated.

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“…Therefore, the architecture requires a router to increase the ports in all directions, which, in turn, increases the cost of the system. Nadooshan et al and Ghosal and Das decrease the diameter of networks by integrating extra links to increase connectivity and implementation cost. Orgas and Marculescu introduced bypass channels between the intermediate nodes for transferring flits in the network, which further shorten the distance between the intermediate nodes within a network.…”

Section: Relevant Researchesmentioning

confidence: 99%

An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design

Poovendran¹,

Sumathi²

2018

Concurrency and Computation

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Summary The incorporation of network‐on‐Chip with communication delivers a strengthening solution to the rising complexity and problems in system‐on‐chip. Here, mesh topology is shortly connected, utilizing the symmetric properties of the network, and is introduced. In addition, 4x4‐Router Architecture–Carry Select Adder (4x4‐RA‐CSLA) method is proposed to improve the function of the Router Architecture (RA) in the network. These features make the system achieve efficient architecture in terms of lower area and power for the interconnection of network scenarios. This new architecture is debugged using ModelSim with Verilog code. The experimental result shows improvement in area and power.

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A Novel Routing Algorithm for On-Chip Communication in NoC on Diametrical 2D Mesh Interconnection Architecture

Cited by 10 publications

References 7 publications

Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine Learning

Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine Learning

Development of routing algorithms in networks-on-chip based on ring circulant topologies

An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design

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