A Novel Scheme for Real-Time Max/Min-Set-Selection Sorters on FPGA

Yan, Di; Wang, Weixing; Zuo, Lei; Xiao-wei, Zhang

doi:10.1109/tcsii.2021.3058245

Cited by 5 publications

(1 citation statement)

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“…As the count-min does not store item keys in its table entries, it cannot be directly used to solve the top-k item query problem. An additional hardware data structure is required to maintain a record of the top key-value tuples [24][25][26]. Only a few FPGA implementations extend the basic functionality of count-min to support the top-k query.…”

Section: Fpga Implementations Of Sketch-based Algorithmsmentioning

confidence: 99%

Finding the Top-K Heavy Hitters in Data Streams: A Reconfigurable Accelerator Based on an FPGA-Optimized Algorithm

Ebrahim

2023

Electronics

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This paper presents a novel approach for accelerating the top-k heavy hitters query in data streams using Field Programmable Gate Arrays (FPGAs). Current hardware acceleration approaches rely on the direct and strict mapping of software algorithms into hardware, limiting their performance and practicality due to the lack of hardware optimizations at an algorithmic level. The presented approach optimizes a well-known software algorithm by carefully relaxing some of its requirements to allow for the design of a practical and scalable hardware accelerator that outperforms current state-of-the-art accelerators while maintaining near-perfect accuracy. This paper details the design and implementation of an optimized FPGA accelerator specifically tailored for computing the top-k heavy hitters query in data streams. The presented accelerator is entirely specified at the C language level and is easily reproducible with High-Level Synthesis (HLS) tools. Implementation on Intel Arria 10 and Stratix 10 FPGAs using Intel HLS compiler showed promising results—outperforming prior state-of-the-art accelerators in terms of throughput and features.

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Section: Fpga Implementations Of Sketch-based Algorithmsmentioning

confidence: 99%