A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

Wei, Wei; Namba, Kazuteru; Kim, Yong-Bin; Lombardi, Fabrizio

doi:10.1109/tc.2015.2462811

Cited by 13 publications

(3 citation statements)

References 33 publications

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“…SEU tolerance can also be improved through a range of layout solutions such as well isolation, increased node spacing, and redundancy. Hardened schemes increase circuit complexity, though they are better able to tolerate SEDU [13,14,[33][34][35][36][37]. A few latch designs are cost-effective while increasing SEU, SEDU, and SET tolerance.…”

Section: Introductionmentioning

confidence: 99%

LIHL: Design of a Novel Loop Interlocked Hardened Latch

Liu

Yu³

et al. 2021

Electronics

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A single event causing a double-node upset is likely to occur in nanometric complementary metal-oxide-semiconductor (CMOS). Contemporary hardened latch designs are insufficient in meeting high reliability, low power consumption, and low delay. This paper presents a novel soft error hardened latch, known as a loop interlocked hardened latch (LIHL). This latch consists of four modified cross-coupled elements, based on dual interlocked storage cell (DICE) latch. The use of these elements hardens the proposed LIHL to soft errors. The simulation results showed that the LIHL has single-event double upset (SEDU) self-recoverability and single-event transient (SET) pulse filterability. This latch also reduces power dissipation and propagation delay, compared to other SEDU or SET-tolerant latches.

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Section: Introductionmentioning

confidence: 99%

LIHL: Design of a Novel Loop Interlocked Hardened Latch

Liu

Yu³

et al. 2021

Electronics

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“…16 nm for Xilinx UltraScale +) and has a higher TID tolerance that make them the usual choice for high-performances and long-term missions. Consequently, many works about SETs in Flashbased FPGAs have been carried out, since SETs in logic gates and wires are one of the main sources of soft errors for these devices [4], [5]. Differently, very few works can be found about SETs in SRAM-based FPGAs, where SEUs in the device configuration memory account for the most part of their errors.…”

Section: Introductionmentioning

confidence: 99%

Analyzing Radiation-Induced Transient Errors on SRAM-Based FPGAs by Propagation of Broadening Effect

et al. 2019

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SRAM-based field programmable gate arrays (FPGAs) are widely used in mission-critical applications, such as aerospace and avionics. Due to the increasing working frequency and technology scaling of ultra-nanometer technology, single event transients (SETs) are becoming a major source of errors for these devices. In this paper, we propose a workflow for evaluating the behavior of SETs in SRAMbased FPGAs. The method is able to compute the propagation-induced pulse broadening (PIPB) effect introduced by the logic resources traversed by transient pulses. Besides, we developed an accurate lookup table (LUT) layout model able to effectively predict the kinds of the SETs induced by radiation-particle and to accurately mimic the phenomena of the SET generation and propagation. The proposed methodology is applicable to any recent technology to provide the SET analysis, necessary for an efficient mitigation technology. The experimental results achieved from a set of benchmark circuits mapped on a 28-nm SRAM-based FPGA and compared with the fault injection experiments demonstrate the effectiveness of our technique. INDEX TERMSFunction generator, propagation induced pulse broadening, LUTs, single event transients, SRAM-based FPGA.

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“…A common solution to figure out the memory operation errors is employing error correction code (ECC), which can detect or (and) correct errors by adding redundant parity check bits [18,19,20,21]. One of the most important parameters of ECC is the error correction and detection (ECD) capabilities.…”

Section: Introductionmentioning

confidence: 99%

Extended coset decoding scheme for multi-bit asymmetric errors in non-volatile memories

Liu

Zhang

et al. 2017

IEICE Electron. Express

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Non-volatile memories (NVMs), such as Magnetic RAM and Resistive RAM, have been considered as the potential working or storage memories in the next generation computer architectures, thanks to the various merits, such as non-volatility, low power and high speed etc. However, new technology brings simultaneously new challenges, e.g. reliability issue, before practical applications. Compared with conventional memories, the errors in NVMs are generally asymmetric, resulting in different failure rates for 0-1 and 1-0 bit flipping. Error correcting codes (ECCs) are common solutions for protecting memories from errors. The most widely used ECCs are the single error correction and double error detection (SEC-DED) codes. Unfortunately, they are primarily designed for correcting symmetric errors and their error correction capabilities are limited to only one bit. Regarding the failure characteristics (e.g., multi-bit and asymmetric) of NVMs, conventional SEC-DED codes are not efficiently applicable. This paper proposes an extended coset decoding scheme for NVMs. Our simulation results with a Hamming code (with Hamming distance of only three) as an example show the effectiveness of the proposed decoding scheme. The proposed decoding scheme can also be extended to other linear block codes and is rather suitable for scenarios with multi-bit asymmetric error features.

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A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

Cited by 13 publications

References 33 publications

LIHL: Design of a Novel Loop Interlocked Hardened Latch

LIHL: Design of a Novel Loop Interlocked Hardened Latch

Analyzing Radiation-Induced Transient Errors on SRAM-Based FPGAs by Propagation of Broadening Effect

Extended coset decoding scheme for multi-bit asymmetric errors in non-volatile memories

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