A novel self-aligned gate process for half-micrometer gate GaAs ICs using ECR-CVD

Shikata, Shinichi; Tsuchimoto, J.; Hayashi, Hideki

doi:10.1109/16.57129

Cited by 3 publications

(2 citation statements)

References 5 publications

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“…In the first one, a gate based on refractory metallization acts as a self alignment element, which can withstand activation high temperature annealing of an ion implanted layer (IIL) at T ≥ 850°С [5][6][7][8][9]. In the second group, a one , two , or three layer dielectric dummy gate is used as a self aligned element, which, on IIL high temperature annealing and diminishing dummy date length, is replaced by a metal gate [9][10][11][12][13][14][15][16][17]. The drawback of the first type of technologies is the significant resistivity of the refractory gate metallization, leading to the degra dation of MESFET frequency characteristics.…”

Section: Introductionmentioning

confidence: 99%

“…One of the cutting edge tech niques enabling one to obtain MESFETs with high per formance is the technique of self aligned device ele ments, particularly, self aligned gate and source and drain contact regions of the transistor [5][6][7][8][9][10][11][12][13][14][15][16][17]. The dis tinctive features of this method are the fact that the res olution of the lithography under use is much higher than the obtained gate length, and that the constitutive operations are performed in the following sequence: Formation of a large sized self aligned element.…”

Section: Introductionmentioning

confidence: 99%

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Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

et al. 2012

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In the present study, a technology for the formation of a submicron GaAs MESFET gate of 0.5-0.1 µm in length and above 0.5 µm in height using a four layer dielectric dummy gate was developed. Tech niques of chemical and plasma chemical deposition from a gaseous phase, differing in etch rates in a buffer solution of hydrofluoric acid, were used to prepare silicon oxide films. Different constructions of a multilayer structure with varying sequences of layers and thicknesses were studied. The conditions of chemical and plasma chemical etching of dielectrics allowing a dummy double T gate to be formed were determined. The employment of a sophisticatedly shaped dummy gate made it possible to obtain a gate electrode of a large cross section with a low length. The possibility in principle to fabricate a MESFET gate with a length of up to Lg = 0.1 µm using lithographic procedures with a minimal resolution of 1.0 µm was demonstrated.

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