A novel SEU hardened SRAM bit-cell design

Abstract

An improved single event upset (SEU) tolerant static random access memory (SRAM) bit-cell with differential read and write capability is proposed. SPICE simulation suggests a more than 1000 times improvement of the critical charge over the standard 6T SRAM cell. With the SEU robustness greatly enhanced at low area and electrical performance costs, the proposed cell is well suited to harsh radiation environment applications such as aerospace and high energy physics.

A novel highly reliable and low-power radiation hardened SRAM bit-cell design

“…The comparison parameters include the critical charge (Q crit ), transistors number, read access time, write access time, power consumption, and area. The Q crit is measured by the above-mentioned current injection way finding the least deposited charge amount which can make the cell upset [13]. Read access time is measured as the time interval from the active word line edge crossing its threshold (50 % of VDD) to bit lines developing 50 mV differential voltage.…”

Design, Application, and Verification of the Novel SEU Tolerant Abacus-Type Layouts

“…To overcome this problem, a few reliable and radiation-hardened units are proposed to protect the nanoscale CMOS circuits in the radiation environments . However, the traditional circuitlevel and system-level redundancies are not optimistic when being implemented to the nanoscale bulk planar technologies to achieve single event upset (SEU) robustness [2,[9][10][11][12][13][14]. For examples, the Quatro 10 T, Quatro 12 T, 14 T, 18 T, and double interlocked storage cell (DICE) structures seem acceptable for their high critical charges of an upset induced by their multiple redundant nodes, while the level of improvements are not dramatic, and even a tendency of continuously decrease of their SEU thresholds with the shrinking of technologies are clearly characterized by recent work, indicating that merely implementing the SEU tolerance units to replace standard cells seems not enough [13][14][15][16][17][18][19][20][21][22][23][24].…”

“…However, the traditional circuitlevel and system-level redundancies are not optimistic when being implemented to the nanoscale bulk planar technologies to achieve single event upset (SEU) robustness [2,[9][10][11][12][13][14]. For examples, the Quatro 10 T, Quatro 12 T, 14 T, 18 T, and double interlocked storage cell (DICE) structures seem acceptable for their high critical charges of an upset induced by their multiple redundant nodes, while the level of improvements are not dramatic, and even a tendency of continuously decrease of their SEU thresholds with the shrinking of technologies are clearly characterized by recent work, indicating that merely implementing the SEU tolerance units to replace standard cells seems not enough [13][14][15][16][17][18][19][20][21][22][23][24]. Therefore, for the nanoscale high-integrated circuits, the effective hardening strategies concerning both the units and peripheral circuits are urgently needed to further improve the SEU tolerance of the existing circuits to satisfy the mission-oriented radiation tolerance.…”

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications

“…On the other hand, the particle may directly strike an OFF-state transistor in a storage element, causing a single-node upset (SNU). Moreover, with the aggressive CMOS technology scaling, circuit integration is becoming much higher and node To mitigate SNUs or even DNUs, using radiation hardening by design (RHBD) techniques, many novel designs of latches [5][6][7] and flip-flops [8][9][10] are proposed, while the other designs mainly consider hardening for static random access memory (SRAM) cells [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. This paper mainly considers hardening for SRAMs.…”