A Novel Si‐B Diffusion Source for p  +  ‐ Poly ‐ Si Gate

Abstract

A p ϩ -poly-Si gate has been proposed for the fabrication of surface-channel p-metal oxide semiconductor field effect transistors (pMOSFETs) in deep submicrometer complementary MOS (CMOS). 1 Surface-channel devices exhibit a better threshold, subthreshold leakage control, and short channel effect control than those of the conventional buried-channel using the n ϩ -poly-Si gate for p-MOSFETs. However, boron, coming from the BF 2 ϩ -implantation, penetrates easily from poly-Si gate through the gate oxide during the following high temperature thermal cycles at the presence of F. 2 To suppress the boron penetration, methods, such as the stacked poly-Si gate, 3 nitrided oxide, 4 oxide gettering, 5 and nitrogen coimplantation 6 have been reported. However, there is little report on the replacement of implantation source (BF 2 ϩ ) by the solid diffusion source. The Si-B film that deposited in the ultrahigh vacuum chemical vapor deposition (UHV/CVD) system has been reported as the polycrystalline structure with extraordinary high B concentration (2 ϫ 10 22 /cm 3 ). 7 Hence, Si-B can be used as a solid diffusion source to form the p ϩ /n diode due to its high B concentration, and the smaller surface concentration and diffusivity. 8 These shallow junctions formed by the Si-B solid diffusion source exhibited better characteristics than those of conventional BF 2 ϩ -implanted junctions in terms of uniformity, ideality factor, and reverse current. In this paper, a novel Si-B layer, for the first time, is proposed as the solid diffusion source for doping the poly-Si as the p ϩ -poly-Si for p-MOSFETs to alleviate the boron penetration problem. It is found that this new process, which is free of F, depicts a better capability of suppressing the boron penetration than conventional methods employing BF 2 ϩ , or B ϩ implantation.Experimental p ϩ -Poly-Si gate MOS capacitors were fabricated on n-type Si(100) wafer with resistivity of 2-4 ⍀ cm. Field oxide, 550 nm, was grown and active areas were defined. A thin gate oxide 9.5 nm was grown at 900ЊC. A 300 nm poly-Si was then deposited. Samples with the conventional p ϩ -poly-Si gate were conducted by implanting BF 2 ϩ , 50 keV, to a dose of 5 ϫ 10 15 cm Ϫ2 ; or B ϩ , 20 keV, to a dose of 5 ϫ 10 15 cm Ϫ2 . While for the Si-B sample, they were put into a UHV/CVD system to deposit a 35 nm Si-B layer using a 1:1 mixture of the pure SiH 4 and B 2 H 6 (1% in H 2 ) at 550ЊC. The base pressure was 2 ϫ 10 Ϫ8 Torr. Afterward, all samples were annealed in a wet O 2 ambient at the temperature between 850 and 950ЊC for 15-35 min. Si-B layer was oxidized in this annealing process to form SiO 2 and the B diffused into the underlying poly-Si gate forming the p ϩ -poly-Si gate. The formed oxides were then dipped away. Al metal was deposited and patterned for contacts. After aluminum metallization, all samples were annealed at 400°C for 30 min in an N 2 ambient to form a good ohmic contact. The comprehensive effects on the annealing temperature (875-950°C) and time (15-35-min) on the p ϩ -In this pape...