A novel SiC superjunction MOSFET with three-level buffer and unipolar channel diode

Cao, Wei; Ying, Sujie; Hu, Xin; Li, Mingyue; Ge, Xinglai; Liu, Dong

doi:10.1016/j.micrna.2022.207420

Cited by 4 publications

(1 citation statement)

References 18 publications

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“…The device structure parameters are summarized in Table 1. Considering the accuracy of the simulation results, many physic models containing the avalanche model (Okuto), anisotropy model, incomplete ionization model, Fermi model, high field velocity saturation model, Auger recombination, and Shockley-Read-Hall (SRH) recombination are adopted in the simulation [19]. The anisotropy model takes into account the differences of material properties in different directions and can better describe the anisotropy of 4H-SiC.…”

Section: Device Structurementioning

confidence: 99%

A Novel Super-Junction DT-MOS with Floating p Regions to Improve Short-Circuit Ruggedness

Yin,

Cao,

et al. 2023

Micromachines

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A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (tsc). The super-junction structure enables the device to possess an excellent compromise of breakdown voltage (BV) and specific on-resistance (Ron,sp). Under short-circuit conditions, the depletion of p-pillar, p-shield, and floating p regions can effectively reduce saturation current and improve short-circuit capability. The proposed device has minimum gate-drain charge (Qgd) and gate-drain capacitance (Cgd) compared with other devices. Moreover, the formation of floating p regions will not lead to an increase in process complexity. Therefore, the proposed MOSFET can maintain good dynamic and static performance and short-circuit ability together without increasing the difficulty of the process.

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Section: Device Structurementioning

confidence: 99%