A Novel Sourceline Voltage Compensation Circuit and a Wordline Voltage-Generating System for Embedded <sc>nor</sc> Flash Memory

Abstract

Key blocks used for embedded NOR Flash memory are introduced in this brief, including a novel sourceline (SL) voltage compensation circuit and a wordline (WL) voltage-generating system. The SL voltage compensation circuit controls the output voltage of the charge pump according to the number of cells to be programmed with data "0" to compensate the IR drop on the SL decoding path. Thus, a stable SL voltage is obtained and high program efficiency with low program disturb is realized. In order to get low power consumption in standby mode and high speed in active mode, a high-performance WL voltage-generating system has been proposed. A 1.8-V 64 × 32 kb embedded NOR Flash memory employing the two techniques has been developed based on a GSMC 0.18-μm 4-poly 4-metal CMOS process. Average standby current of the embedded Flash memory IP circuit less than 0.3 μA is achieved at 1.8 V and 25 • C.

Area-efficient charge pump with local boost technique for embedded flash memory

“…In recent decades, the growing portable equipment market has created a strong demand for embedded flash (eFlash) memories due to the merits of high security, small size, low cost, and low power consumption [1]. Low chip area has become a key design aspect for eFlash memories.…”

“…Low chip area has become a key design aspect for eFlash memories. Since the high voltage is supplied by onchip charge pump (CP) [2], the complicated operation voltage feature of eFlash memories [1,3] requires large area penalty of CP. Several designs of charge pump targeting smaller size and higher output capability have been proposed [3,4,5,6].…”