A Novel Structure for Improving Erase Performance of Vertical Channel NAND Flash With an Indium-Gallium-Zinc-Oxide Channel

Choi, Seonjun; Kim, Bongsueg; Jeong, Jae Kyeong; Song, Yun Heub

doi:10.1109/ted.2019.2942935

Cited by 19 publications

(21 citation statements)

References 14 publications

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“…In addition, even if the GSL was kept in the off state, the leakage current did not decrease at all, and the high current of 10 −8 A was maintained. This result is very different from the very low leakage current (10 −15 A) of the IP structure that we previously published [15]. Contrary to expectations, the proposed FF structure did not seem to show the low leakage current characteristic of the IGZO channel.…”

Section: Simulation Results and Discussioncontrasting

confidence: 99%

“…To solve this problem, we studied an IGZO-nitride-P type filler (INP) structure and an IGZO-P type filler (IP) structure in previous studies and verified these structures through device simulations. The proposed INP and IP structures have an added P-type filler (Pfiller) in the center of the holes in the V-NAND structure [15]. This filler is connected to the P-sub region at the bottom of the structure to facilitate the rapid transport of hole carriers, thereby assisting in maintaining high voltage across the entire channel during the erase operation.…”

Section: Introductionmentioning

confidence: 99%

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Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure

Choi

Jeong

et al. 2021

Electronics

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In this study, we developed a V-NAND with an improved IGZO-P type (IP) floating filler (FF) structure based on an IGZO channel verified in previous studies and demonstrated that it has a very fast erase speed through device simulation. The proposed FF structure can supply holes generated through the Gate-Induced Drain Leakage (GIDL) phenomenon in the upper polysilicon string select line (SSL) channel to the IGZO channel through a P-type filler, and the structure proposed by this operation shows a very fast erase speed of 4 μs. A fast erase speed was achieved because the filler adjacent to the IGZO channel, like IP structures in previous studies, functioned as a path through which electrons emitted from the charge storage layer moved easily, rather than simply supplying holes. This assumption was confirmed by assessing the change in electron density of the channel during the erase operation. Next, we investigated the optimum conditions for leakage current reduction through various condition changes of the lower ground select line (GSL) gate in the proposed structure. We confirmed that the leakage current of the proposed structure can be minimized by changing the number of lower GSL gates, changing the length of the GSL channel, and/or changing the work function of the GSL gate material. We obtained a leakage current of 10−17 A when the GSL channel was 480 nm long with six GSL gates, each with a length of 40 nm. The work function of the gates was 4.96 eV.

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Section: Simulation Results and Discussioncontrasting

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure

Choi

Jeong

et al. 2021

Electronics

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“…The extremely low off-current of the oxide semiconductors made them candidates to replace silicon semiconductors in memory, and studies on this topic increased. Various research on DOSRAM [32,33], and other devices such as charge trap devices [34], vertical-NAND (V-NAND) [35], monolithic 3D DRAM [36], vertical Fe-NAND [37], and CAA field effect transistors (FETs) [30] have been reported to date, as shown in figure 1(d). However, insufficient on-current, the low device stability of the AOS-TFT, and sputtering-based processes are huge barriers to further expansion in display and memory fields, and still need to be overcome.…”

Section: History Of Oxide Semiconductor Tfts In Display and Memory In...mentioning

confidence: 99%

Atomic layer deposition for nanoscale oxide semiconductor thin film transistors: review and outlook

Kim

Kim²,

Kim³

et al. 2023

Int. J. Extrem. Manuf.

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Since the report of amorphous In-Ga-Zn-O (a-IGZO) based thin film transistors (TFTs), interest in oxide semiconductors has increased due to their high mobility, low off-current, low process temperature, and wide flexibility of compositions and processes. However, oxide semiconductors deposited by conventional processes like physical vapor deposition (PVD) leads a problematic issue to produce high-resolution displays and highly integrated memory devices due to the limited process flexibility and the poor conformality on the structured surface. Thus, a need to replace conventional deposition processes has emerged. Atomic layer deposition (ALD) is an advanced technique which could provide conformal, thickness-controlled, and high-quality thin film deposition. From these backgrounds, recently, studies on ALD based oxide semiconductors have dramatically increased. Even so, the relations of film properties of ALD-oxide semiconductors with the main variables associated with deposition and issues related to applications are still less understood than conventional one. In this review, we introduce ALD-oxide semiconductors by providing: (Ⅰ) a brief history and importance of ALD-based oxide semiconductors in the industry, (Ⅱ) a discussion of the value of ALD in oxide semiconductors (in-situ composition control in vertical distribution /vertical structure engineering / chemical reaction and film properties / insulator and interface engineering), and (Ⅲ) an explanation of the challenging issues of scaling oxide semiconductors and ALD in industrial applications. This review provides a valuable perspective for researchers who have interest in semiconductor material and electronic devices by suggesting the reasons why ALD is important in the application of oxide semiconductors.

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“…Besides, sidewall engineering with stacking of each functional layers is an essential technology to realize a 3D architecture device. [20][21][22] In this point of view, conventional sputtering has a drawback of step coverage because atoms and/or molecules from sputtering targets are directionally deposited. Atomic layer deposition (ALD) is considered to be a promising deposition technique to enhance electrical properties and step-coverage due to self-limiting reactions on the surface of the substrate.…”

Section: Introductionmentioning

confidence: 99%

“…Besides, sidewall engineering with stacking of each functional layers is an essential technology to realize a 3D architecture device. [ 20–22 ]…”

Section: Introductionmentioning

confidence: 99%

Exploration of Chemical Composition of In–Ga–Zn–O System via PEALD Technique for Optimal Physical and Electrical Properties

Hong

Kim

Choi

et al. 2023

Adv Elect Materials

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In–Ga–Zn–O (IGZO) material has been researched due to its favorable electrical characteristics for application in thin‐film transistor (TFT) applications such as low off current and relatively high mobility. However, most recently, as the developing and expanding application fields, conventional IGZO is a challenging aspect because higher mobility and excellent step‐coverage are required to be applied to high‐resolution displays and 3D NAND. In this regard, atomic layer deposition (ALD) is suggested as a novel deposition method for tackling issues. Here, this work systematically synthesizes IGZO films with various compositions by the supercycle technique of plasma‐enhanced ALD (PEALD) to determine the optimum metal cation composition range of the IGZO system for high‐mobility TFTs. The trends in the metal composition dependent electrical properties of ALD processed IGZO films are comparable to the previously reported results, while the structural properties are exclusive. Since both microstructure and carrier concentration affect to device characteristics complexly, the optimal In–Ga–Zn region is newly demonstrated via PEALD (XIn: 0.56–0.63, XGa: 0.13–0.17, XZn: 0.17–0.34). In this region, the device exhibits a remarkably high µFE of 41.4–43.7 cm2 V−1 s−1, a low subthreshold swing (SS) of 0.24–0.25 V decade−1, an initial threshold voltage (Vth) of −0.9 to −1.0 V, and a slight Vth shift (0.01 V) under the positive bias temperature stability (PBTS).

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A Novel Structure for Improving Erase Performance of Vertical Channel NAND Flash With an Indium-Gallium-Zinc-Oxide Channel

Cited by 19 publications

References 14 publications

Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure

Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure

Atomic layer deposition for nanoscale oxide semiconductor thin film transistors: review and outlook

Exploration of Chemical Composition of In–Ga–Zn–O System via PEALD Technique for Optimal Physical and Electrical Properties

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