2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2018
DOI: 10.1109/icecs.2018.8617859
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A novel sub-10 ps resolution TDC for CMOS SPAD array

Abstract: In this work, we present a novel Time-to-Digital Converter (TDC) for single-chip integration in Single-Photon Avalanche-Diode (SPAD) array and digital Silicon Photomultiplier (SiPM). Such novel detector-timing electronics combination will be suitable for Time-Correlated Single-Photon Counting (TCSPC) applications and direct Time-Of-Flight (TOF) measurements. The proposed TDC is based on a 200 MHz 4-bit counter that guarantees a Full-Scale Range of 80 ns. Two interpolators exploit the sliding scale technique to… Show more

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Cited by 8 publications
(6 citation statements)
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“…The implemented TDCs are based on an architecture employing a multiphase clock interpolation based on a Delay-Locked Loop (DLL) [28], [29], which generates 16 clock phases from a 400 MHz reference clock; each of these clock phases is delayed by 78 ps from one another. Each 16 clock phases can be tuned, to compensate any delay mismatch, thus improving the overall TDC linearity.…”
Section: Smart Tdc Sharingmentioning
confidence: 99%
“…The implemented TDCs are based on an architecture employing a multiphase clock interpolation based on a Delay-Locked Loop (DLL) [28], [29], which generates 16 clock phases from a 400 MHz reference clock; each of these clock phases is delayed by 78 ps from one another. Each 16 clock phases can be tuned, to compensate any delay mismatch, thus improving the overall TDC linearity.…”
Section: Smart Tdc Sharingmentioning
confidence: 99%
“…Since the single-shot precision is dominated by the 3 ns laser FWHM (variance σ = 1.27 ns), the Least-Significant Bit (LSB) of the TDC must be set shorter in order to make its σ TDC uncertainty contribution negligible with respect to the laser variance σ laser (see Equation (2). An LSB of about 100 ps or slightly shorter can be easily implemented in cost-effective CMOS technology [12,31], so to possibly allow for the exploitation of even better (shorter pulse) and more expensive lasers.…”
Section: Tdc Performancementioning
confidence: 99%
“…The FSR of the TDC is set by the maximum distance range to be detected, which is at least 1 m in our application (i.e., a TOF of 6.7 ns); thus, 10 ns FSR is a reasonable value, with a corresponding low number of bits (6–7 bits, given the 10 ns FSR and about 100 ps LSB), so a coarse TDC suffice, with no need to implement a finer TDC architecture [ 12 , 31 ].…”
Section: Required Detector Performancementioning
confidence: 99%
“…Photoelectrons generated by the absorption of individual photons are accelerated by the strong electric field in the diode and undergo an avalanche multiplication process that produces a macroscopic, measurable current through the device [10]. Events detected by the SPAD pixels are often timed on-chip using combinations of time-to-analog converters (TACs) and analog-to-digital converters (ADCs) [11,12], or time-to-digital converters (TDCs) [13][14][15], to produce a digital representation of the time of arrival of each detected photon, called a timestamp. Each timestamp T ts is a measure of the time of arrival of a photon detected by the pixel T pixel relative to the generation time of the laser pulse T 0 , according to the relation…”
Section: Tcspc Lidarmentioning
confidence: 99%