A novel symmetrical split-gate structure for 2-bit per cell flash memory

Abstract

A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection (SSI) and a poly-to-poly tunneling mechanism respectively.

Temperature-insensitive reading of a flash memory cell

“…This thermal-induced effect can sometimes be useful, such as in designing temperature sensors or temperature memories [1] , but in most cases of flash applications, this thermal effect is considered undesirable because it gives bad working performances and various reliability issues [2−4] . Many methods have been proposed to avoid the temperature effect, such as adding extra peripheral circuits providing temperature bias control signals to improve voltage distribution [5,6] , using dummy cells as references to compensate for the temperature effect of current [7,8] , or resorting to complicated algorithms [9] . However, these methods consume much power and area and reduce storage capacity.…”

Design, modelling, and simulation of a floating gate transistor with a novel security feature

“…Non-volatile memories have many applications, including industrial, military, and general public [1−3] . A floating gate transistor (FGT) can be used to store a bit of information [4,5] . For instance, in an FGT, the transistor is a metal-oxide semiconductor field-effect transistor (MOSFET) with a floating gate (FG) that can either be charged by positive or negative charges to represent an on or off switch [6,7] .…”