Reversible circuits are a possible alternative to conventional circuits because they have the same input and output and avoid power loss due to bit erasure operations. It has been widely used in various research areas such as optical computing, low-power CMOS design, DNA computing, quantum computing and thermodynamic techniques. In this paper, we suggest a novel design for a 16-bit floating-point reversible adder/subtractor that is complied with IEEE-754 standard. This design proposes the use of signal control bits to determine whether to add or subtract floating-point numbers, thereby increasing the operation speed. The key to reducing quantum cost, constant input, and garbage output lies in the design of reusable components. Finally, the feasibility of the design is verified by FPGA.