A novel synthesis approach for active leakage power reduction using dynamic supply gating

Bhunia, S.; Banerjee, N.; Chen, Q.; Mahmoodi, H.; Roy, K.

doi:10.1109/dac.2005.193857

Cited by 6 publications

(21 citation statements)

References 6 publications

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“…However, for two benchmarks namely, cht and cm]50a, we observed area improvement. This is mainly due to better optimization after control variable isolation and multilevel Shannon expansion [8].…”

Section: Simulation Resultsmentioning

confidence: 99%

“…f (Xl,...,x,,...,x,) =xxj.CF +x-.CF+-xj.CF3 + .CF (7) Control variable selection plays a very important role in achieving desired goals in Shannon's expansion based partitioning. In [8,9], the most binate variable is chosen as control variable to minimize the area overhead. However, this heuristic may not lead to the confinement of critical paths of the circuit after expansion.…”

Section: Design Methodologymentioning

confidence: 99%

“…Using this metric, we follow the steps described in [8] for choosing the control variable in our synthesis flow. To achieve the dual objectives of isolating the critical paths to a cofactor while reducing its activation probability during partitioning and synthesis, we adhere to following approach: (a) we partition the circuit and determine the cofactor where the critical paths have been isolated (called critical cofactor); (b) we mark this cofactor (i.e.…”

Section: Max(ai Bi)mentioning

confidence: 99%

“…ICCAD'06, November [5][6][7][8][9]2006, San Jose, CA Copyright 2006 ACM 1-59593-38941/06/0011...$5.00 confinement of critical paths of synthesized design to known logic block (or cofactor, as we will see later). Such isolation leads to a design methodology for low power dissipation by making the critical paths predictable and rare under parametric variations.…”

Section: Introductionmentioning

confidence: 99%

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A New Paradigm for Low-power, Variation-Tolerant Circuit Synthesis Using Critical Path Isolation

Ghosh¹,

Bhunia²,

Roy³

2006

2006 IEEE/ACM International Conference on Computer Aided Design

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Design considerations for robustness with respect to variations and low power operations typically impose contradictory design requirements. Low power design techniques such as voltage scaling, dual-Vth etc. can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variationtolerant circuit design, which allows aggressive voltage scaling. The principal idea is to (a) isolate and predict the set ofpossible paths that may become critical under process variations, (b) ensure that they are activated rarely, and (c) avoid possible delay failures in the critical paths by dynamically switching to two-cycle operation (assuming all standard operations are single cycle), when they are activated. This allows us to operate the circuit at reduced supply voltage while achieving the required yield. Simulation results on a set of benchmark circuits at 70nm process technology show average power reduction of 60% with less than 10% performance overhead and 18% overhead in die-area compared to conventional synthesis. Application of the proposed methodology to pipelined design is also investigated.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Design Methodologymentioning

confidence: 99%

Section: Max(ai Bi)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A New Paradigm for Low-power, Variation-Tolerant Circuit Synthesis Using Critical Path Isolation

Ghosh¹,

Bhunia²,

Roy³

2006

2006 IEEE/ACM International Conference on Computer Aided Design

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“…The few techniques proposed in the area of Runtime Leakage Reduction [5], [6] were based on either new synthesis approaches, or using clock signal to apply supply gating to selected gates. This work aims at operating directly on the post synthesis netlists using industry-based standard libraries, and without the aid of clock signal.…”

Section: Introductionmentioning

confidence: 99%

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction

Potluri

Chandrachoodan

Kamakoti

2011

2011 IEEE Computer Society Annual Symposium on VLSI

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We consider the problem of reducing active mode leakage power by modifying the post-synthesis netlists of combinational logic blocks. The stacking effect is used to reduce leakage power, but instead of a separate signal one of the inputs to the gate itself is used. The approach is studied on multiplier blocks. It is found that a significant number of nets have high probabilities of being constant at 0 or 1. In specific applications such as those having high peak to average ratio, like audio and other signal processing applications, this effect is more pronounced. We show how these signals can be used to put gates to sleep, thus saving significant leakage power.

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A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation

Ghosh

Bhunia

Roy

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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Design considerations for robustness with respect to variations and low power operations typically impose contradictory design requirements. Low power design techniques such as voltage scaling, dual-V th etc. can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variationtolerant circuit design, which allows aggressive voltage scaling. The principal idea is to (a) isolate and predict the set of possible paths that may become critical under process variations, (b) ensure that they are activated rarely, and (c) avoid possible delay failures in the critical paths by dynamically switching to two-cycle operation (assuming all standard operations are single cycle), when they are activated. This allows us to operate the circuit at reduced supply voltage while achieving the required yield. Simulation results on a set of benchmark circuits at 70nm process technology show average power reduction of 60% with less than 10% performance overhead and 18% overhead in die-area compared to conventional synthesis. Application of the proposed methodology to pipelined design is also investigated.

show abstract

A novel synthesis approach for active leakage power reduction using dynamic supply gating

Cited by 6 publications

References 6 publications

A New Paradigm for Low-power, Variation-Tolerant Circuit Synthesis Using Critical Path Isolation

A New Paradigm for Low-power, Variation-Tolerant Circuit Synthesis Using Critical Path Isolation

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction

A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation

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