2015
DOI: 10.1016/j.mee.2015.04.111
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A novel technique exploiting C–V, G–V and I–V simulations to investigate defect distribution and native oxide in high-κ dielectrics for III–V MOSFETs

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Cited by 9 publications
(6 citation statements)
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“…The uniform defect distribution along the dielectric thickness ( N bulk ) is responsible for the trap‐assisted tunnelling (TAT) regime at low voltages, while the two near‐interface defect distributions ( N ni ) facilitate electron tunnelling at high fields. Minor discrepancies between measurements and simulations could be improved by further optimizing the shapes of the defect distributions, which is however out of the scope of this paper . These defects were considered to be associated with O vacancies because of their specific parameters (e.g.…”
Section: Methodsmentioning
confidence: 99%
“…The uniform defect distribution along the dielectric thickness ( N bulk ) is responsible for the trap‐assisted tunnelling (TAT) regime at low voltages, while the two near‐interface defect distributions ( N ni ) facilitate electron tunnelling at high fields. Minor discrepancies between measurements and simulations could be improved by further optimizing the shapes of the defect distributions, which is however out of the scope of this paper . These defects were considered to be associated with O vacancies because of their specific parameters (e.g.…”
Section: Methodsmentioning
confidence: 99%
“…The simulation-based spectroscopy is used to profile the defect distributions in a 1nm SiO x /5nm HfO 2 MOSFET with Si substrate. In order to identify the regions where defect effect is maximum on IV and BTI curves, we adopted the sensitivity maps (15). These maps are calculated by moving a narrow defect density distribution along a matrix of bin resulting from the discretization in space and energy of the dielectric stack.…”
Section: Si-mosfet Hk Gate Stackmentioning
confidence: 99%
“…The developed spectroscopic technique is based on the iterative procedure sketched in Fig. 4 (15), which relies on the interpretation in a consistent defect scenario of CV, GV and IV. Using complementary measurements allows widening the region within the dielectric bandgap along the thickness where defects can be profiled.…”
Section: Si-mosfet Hk Gate Stackmentioning
confidence: 99%
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