A Novel Technique to Investigate the Impact of Temperature and Process Parameters on Electrostatic and Analog/RF Performance of Channel Modulated Junctionless Gate-all-around (CM-JL-GAA) MOSFET

Gupta, Abhinav; Gupta, Vidyadhar; Pandey, Amit Kumar; Gupta, Tarun Kumar

doi:10.1007/s12633-022-01794-5

Cited by 5 publications

(3 citation statements)

References 34 publications

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“…The investigation of temperature ranging from 200 K to 500 K is particularly relevant due to the diverse range of temperaturesensitive applications in electronics [22] and biomedicine [23]. Other reports are also available that have investigated the impact of temperature on similar ranges [24,25].…”

Section: Introductionmentioning

confidence: 99%

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

Bharti,

Mittal

2024

Phys. Scr.

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An Improved Junctionless Nanowire Field Effect Transistor (I-JL-NWFET) device is proposed in this paper to address the limitations of conventional JL-NWFET. This research paper initially, comprehensively analyzes the impact of channel length (L) and channel thickness (t si ) scaling on the electrical, analog/RF, and linearity performance of I-JL-NWFET and JL-NWFET. The results suggest that the specific design features in I-JL-NWFET contribute to a more robust and less sensitive response to variations in scaling compared to its counterpart, JL-NWFET. Furthermore, an exploration into the impact of temperature on the electrical, analog/RF, and linearity performance is also conducted for both I-JL-NWFET and JL-NWFET. The electrical performance of I-JL-NWFET showcases a significantly reduced temperature sensitivity in parameters like drain current (I D ), Subthreshold Slope (SS) and Drain Induced Barrier Lowering (DIBL) compared to JL-NWFET. Subsequently, analyzing the analog/RF performance in the context of parameters such as transconductance (g m ), Transconductance Gain Factor (TGF), output conductance (g d ), early voltage (V EA ), total gate capacitance (C GG ), and cut-off frequency (f T ) under temperature variation, a lower degree of variability in I-JL-NWFET is observed compared to JL-NWFET. Furthermore, the linearity performance of I-JL-NWFET, assessed through parameters such as second and third-order transconductance (g m2 , g m3 ), second and third-order input voltage intercept points (VIP2, VIP3), and third-order intermodulation distortion (IIP3 and IMD3) is improved at the higher temperature than that of JL-NWFET.

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Section: Introductionmentioning

confidence: 99%

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

Bharti,

Mittal

2024

Phys. Scr.

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“…As pitch sizes decrease, the need for enhanced fin structures with increased compactness, height, and slender design arises, posing concerns for both performance and manufacturing processes. [7][8][9] On the other hand, gate-all-around nanowire transistors (GAA NW-FETs) are expected to enhance device scaling due to their exceptional ability to control short channels and achieve high current density. GAA NW-FETs have emerged as a promising option for sub-7 nm technology nodes due to their superior electrostatic integrity compared to FinFETs and TFETs.…”

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confidence: 99%

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Beebireddy,

Fatima,

2024

ECS J. Solid State Sci. Technol.

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This comprehensive study delves into the intricate analysis of the electrical and analog/RF performance of the Dual Material (DM) junctionless (JL) Tree-FET. During the optimization process, various DC and analog/RF metrics were taken into account. It is observed that, as the gate length decreases (12 nm to 8 nm), there is an increment in drain induced barrier lowering (DIBL), switching ratio (Ion/Ioff), and subthreshold swing (SS). Conversely, reducing the size of TNS (and WNS) from 10 nm to 5 nm (and 20 nm to 10 nm, respectively) lead to notable improvements, with a 34.4% (21.01%) decrease in SS, 93.19% (58.86%) decrease in DIBL, and 98.6% (41.06%) increase in Ion/Ioff. Furthermore, the analog/RF performance metrics of the device is carefully examined across dimensional variations, revealing significant improvements at the optimal values. Additionally, the study extends to the evaluation of inverter circuit characteristics with DM JL Tree-FET. Remarkably, the static noise margin (SNM) and delay exhibit 337.3 mV and 3.053 ps, respectively, positioning the device as a prime candidate for applications demanding low power consumption and high-frequency operation in future technology nodes.

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“…Moreover, the authors identified that the rise in temperature enhances the wireless performance. Abinav Gupta et al 16 analyzed the impact of temperature on junctionless GAA FET and described that analog/RF parameters are marginally affected with graded channel. Himanshi Awasthi et al 17 analyzed the analog and RF performance of dielectric pocket GAA FET with variation of temperature.…”

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confidence: 99%

Temperature Analysis of DMGC CGAA FET for Future Deep Space and Military Applications: An Insight into Analog/RF/Self-Heating/Linearity

Mudidhe

Nistala

2023

ECS J. Solid State Sci. Technol.

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This manuscript introduces a pioneering investigation on the temperature effects of Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET by outlining its significance in various aspects such as analog/RF, self-heating, and linearity performance metrics. For this analysis, we have proposed a DMGC CGAA FET by amalgamating the gate and channel engineering techniques and the temperature is varied from 250K to 450K. A significant improvement in Ion/Ioff, SS, and DIBL by an amount of 96.98%, 19.49%, and 51.26% is obtained respectively for the proposed DMGC CGAA FET as compared to the single material graded channel (SMGC) CGAA FET. As the temperature is reduced from 450K to 250K, a noticeable improvement in analog/RF figure of merits and delay is obtained. Further, the self-heating effect (SHE) analysis revealed that the utilization of lower Rth is preferrable to minimize SHE in the device. Moreover, linearity parameters like gm2, gm3, VIP2, VIP3, IIP3 and IMD3 are noticed to be better for lower temperatures at higher VGS indicating good linearity. The obtained results make proposed device an ideal choice for various applications especially that operate in low temperature environments such as deep space, military, and RF applications.

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A Novel Technique to Investigate the Impact of Temperature and Process Parameters on Electrostatic and Analog/RF Performance of Channel Modulated Junctionless Gate-all-around (CM-JL-GAA) MOSFET

Cited by 5 publications

References 34 publications

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

Optimizing Device Dimensions for Dual Material Junctionless Tree-FET: A Path to Improved Analog/RF Performance

Temperature Analysis of DMGC CGAA FET for Future Deep Space and Military Applications: An Insight into Analog/RF/Self-Heating/Linearity

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