A novel testing approach for full-chip CDM characterization

WCDM2 — Wafer-level charged device model testing with high repeatability

“…Several test methods have been introduced for generating charged device model (CDM) stress at the wafer level [1]- [4]. Wafer-level testing is desirable for multiple reasons, including reliability assessment earlier in the design phase (before packaging), elimination of packaging cost, and elimination of unrealistic package parasitics when stressing small test structures.…”