A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks

Abstract

We propose a novel ultra-low-power, voltage-based compute-in-memory (CIM) design with a new single-ended 8T SRAM bit cell structure. Since the proposed SRAM bit cell uses a single bitline for CIM calculation with decoupled read and write operations, it supports a much higher energy efficiency. In addition, to separate read and write operations, the stack structure of the read unit minimizes leakage power consumption. Moreover, the proposed bit cell structure provides better read and write stability due to the isolated read path, write path and greater pull-up ratio. Compared to the state-of-the-art SRAM-CIM, our proposed SRAM-CIM does not require extra transistors for CIM vector-matrix multiplication. We implemented a 16 k (128 × 128) bit cell array for the computation of 128× neurons, and used 64× binary inputs (0 or 1) and 64 × 128 binary weights (−1 or +1) values for the binary neural networks (BNNs). Each row of the bit cell array corresponding to a single neuron consists of a total of 128 cells, 64× cells for dot-product and 64× replicas cells for ADC reference. Additionally, 64× replica cells consist of 32× cells for ADC reference and 32× cells for offset calibration. We used a row-by-row ADC for the quantized outputs of each neuron, which supports 1–7 bits of output for each neuron. The ADC uses the sweeping method using 32× duplicate bit cells, and the sweep cycle is set to 2N−1+1, where N is the number of output bits. The simulation is performed at room temperature (27 °C) using 45 nm technology via Synopsys Hspice, and all transistors in bitcells use the minimum size considering the area, power, and speed. The proposed SRAM-CIM has reduced power consumption for vector-matrix multiplication by 99.96% compared to the existing state-of-the-art SRAM-CIM. Furthermore, because of the decoupled reading unit from an internal node of latch, there is no feedback from the reading unit, with read static noise, and margin-free results.

Binarized neural network of diode array with high concordance to vector–matrix multiplication

“…Compared to other memory devices used as components of emerging BNNs 11 – 21 , the p + -n-p-n + diodes operating by the positive-feedback loop mechanisms have a significant advantage in terms of reliability and endurance since the relatively low operating voltage prevents the deterioration of devices under sustained operations. Furthermore, the BNN comprising the p + -n-p-n + diodes can be more simplified than those designed by SRAMs and DRAMs 18 , 33 . In this study, we demonstrate BNNs with 4 × 1 and 2 × 2 arrays, consisting of p + -n-p-n + diodes.…”

A single ended, single port configuration based 9 T SRAM cell for stability enhancement

“…Recent advancements in AI, such as facial recognition and video recognition, have significantly eased the burden on human intelligence. These improvements have been largely driven by neural networks, which utilize massive datasets to train their processors leading to enhanced accuracy [1]. These processors incorporate an on-chip random access memory (RAM) which necessitates low dynamic power and high-speed static RAM (SRAM).…”