A Novel Voltage Level-Up Shifter Design for Power Efficient Methods Using Dual Current Mirror Technique

PramodKumar, Aylapogu; Kalivaraprasad, B.; Prasad, M. V. D.; Jayalakshmi, A.; Ravichand, S.

doi:10.1007/978-981-19-2828-4_61

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Minimizing Short Current Power1

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2023

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“…By utilising a technique known as split route, in which PMOS and NMOS transistors are driven by different signals, the potential for a short between P type and N type elements in the circuit can be mitigated or even removed entirely (Nagarajan,P etal 2016). During a short circuit, this method is helpful for lowering the amount of power that MOS and CNTFET-based circuits and systems need to draw from their batteries [18].…”

Section: Minimizing Short Current Powermentioning

confidence: 99%

A Review on low-Power VLSI CMOS and CNTFET Circuits

Gopathoti¹,

Pendyala²

2023

IJSMEM

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Nowadays, power consumption is one of the primary considerations in the design of VLSI (Very Large Scale Integration) circuits based on complementary metal oxide semiconductors (CMOS) and carbon nanotube field effect transistors (CNTFET). This is because of the present circumstance. The fundamental reason for this is that power utilisation has been raised to the status of a top priority due to the improvements in integration and scaling as well as the constant increases in operating frequency. Additional power consumption from circuits and designs makes them challenging to implement in portable devices. The quantity of power lost during operation has an immediate effect on the cost of packaging the IC and systems. A variety of power dissipation sources and low power VLSI design strategies for CMOS and CNTFET-based circuits are discussed in this article.

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Section: Minimizing Short Current Powermentioning

confidence: 99%