A novel write method for improving RESET distribution of PRAM

Park, H. K.; Lee, K. W.; Song, Seunghyun; Lee, K. G.; Shin, Jungyeop; Gangasani, V.; Shin, Younghak; Kang, Dae-Hwan; Park, J. H.; Song, Kihyung; Koh, G.H.; Jeong, Goojin; Park, K. T.; Kyung, Kye-Hyun

doi:10.23919/vlsit.2017.7998209

Cited by 4 publications

(3 citation statements)

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“…For a cross-point Ge-doped SbTe (Ge-ST) phase-change random access memory (PCM)-cell array, a confined memory-cell structure is essential [1,[9][10][11][12][13]. A cross-point Ge-ST PCM-cell array is fabricated with the ALD of a Ge-ST film on the contact hole isolated with a spacer material (i.e.…”

Section: Discussionmentioning

confidence: 99%

“…However, the GST-based PCM fundamentally has two critical challenges: to reduce the RESET current and increase the SET speed. To reduce the RESET current via minimizing 3D memory-cell volume, a confined memory-cell structure has been proposed [9][10][11][12][13][14]. Note that the confined memory cell has a vertical stacked structure in which the bottom electrode/contact hole is filled by a GST material/top electrode.…”

Section: Introductionmentioning

confidence: 99%

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Surface-tensile-stress induced polishing-voids in cross-point phase-change-memory cells: corrosion mechanism and solution

Kim

Cui

Cho

et al. 2019

Semicond. Sci. Technol.

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In the fabrication of cross-point phase-change-memory-cells through atomic-layer-deposition of Ge-doped SbTe (Ge-ST) film followed by chemical-mechanical-polarization (CMP), a remarkable surface tensile stress was generated, originating from the surface stress induced by the pad down force and the surface structure tensile stress in a confined memory-cell structure. It was maximized at the position of the Si 3 N 4 -film spacer where the curvature becomes zero. The maximized surface tensile stress produced polishing induced voids via the generation mechanism of the stress corrosion cracking. The generation frequency and nanoscale size of the polishing induced voids rapidly increased at the maximum surface tensile stress during CMP. Then, they slightly decreased and saturated when the surface tensile stress reduced during further CMP. A design of a spacer using a SiO 2 -film spacer rather a Si 3 N 4 -film spacer could prevent the generation of the polishing induced voids, confirming that the generation mechanism of the polishing induced voids is associated with the stress corrosion cracking.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Surface-tensile-stress induced polishing-voids in cross-point phase-change-memory cells: corrosion mechanism and solution

Kim

Cui

Cho

et al. 2019

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…On the other hand, some circuit design techniques can be introduced to mitigate the snapback current ( Kim & Ahn, 2005 ; Redaelli et al, 2004 ; Parkinson, 2011 ). Also, circuit designers can propose variation-tolerant or variation-compensated techniques to address the variation issue ( Athmanathan et al, 2016 ; Park et al, 2017 ; Hwang et al, 2010 ; Bae et al, 2018 ), or sneak-current cancellation scheme for the sneak current issue ( Vontobel et al, 2009 ; Shevgoor et al, 2015 ; Bae et al, 2016 ). In addition, looking further forward, RRAM is regarded to be a promising candidate for in-memory computing or neuromorphic computing, because of its capability to store analog weights ( Alibart, Zamanidoost & Strukov, 2013 ; Prezioso et al, 2015 ; Yoo, 2019 ; Xue et al, 2019 ; Kim & Williams, 2019 ; Yoon, Han & Bae, 2020 ; Wang et al, 2019 ).…”

Section: Memory and Storagementioning

confidence: 99%

Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

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Due to the explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and interconnect) have started facing their limits, and therefore are not as effective as they used to be and are also expected to reach the end in the near future. Evidently, it is a large challenge for computer hardware industry. However, at the same time it also provides great opportunities for the hardware design industry to develop novel technologies and to take leadership away from incumbents. This paper reviews the technical challenges that today’s computing systems are facing and introduces potential directions for continuous advancement of computing capability, and discusses where computer hardware designers find good opportunities to contribute.

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A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy Operation

Park

Jung

2018

2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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A novel write method for improving RESET distribution of PRAM

Cited by 4 publications

References 1 publication

Surface-tensile-stress induced polishing-voids in cross-point phase-change-memory cells: corrosion mechanism and solution

Surface-tensile-stress induced polishing-voids in cross-point phase-change-memory cells: corrosion mechanism and solution

Today’s computing challenges: opportunities for computer hardware design

A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy Operation

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