A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance

Sloan, Joseph; Kesler, David; Kumar, Rakesh; Rahimi, Asgar Bradaran

doi:10.1109/dsn.2010.5544923

Cited by 37 publications

(25 citation statements)

References 15 publications

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“…It is, therefore, essential to develop simulation and emulation infrastructures for UnO computing systems which are scalable while retaining variability modeling accuracy. The work in this direction has been somewhat limited (e.g., [77] in context of performance variability for a specific system or error emulation in [19], [63]) and a key challenge for UnO software methods is building such emulation platforms for large class of computing systems which model all manifestations (error, delay, power, aging, etc.) of variability.…”

Section: F Variability Simulation Challengesmentioning

confidence: 99%

“…In context of erroneous UnO machines, several alternatives exist ranging from detecting and then correcting faults within the application as they arise (e.g., [61], [62]) to designing applications to be inherently error-tolerant (e.g., application robustification [63]). In addition, many applications have inherent algorithmic and cognitive error tolerance.…”

Section: B Software Adaptations For Quality-complexity Tradeoffsmentioning

confidence: 99%

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Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Gupta

Agarwal

Dolecek

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

138

116

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Abstract-Microelectronic circuits exhibit increasing variations in performance, power consumption, and reliability parameters across the manufactured parts and across use of these parts over time in the field. These variations have led to increasing use of overdesign and guardbands in design and test to ensure yield and reliability with respect to a rigid set of datasheet specifications. This paper explores the possibility of constructing computing machines that purposely expose hardware variations to various layers of the system stack including software. This leads to the vision of underdesigned hardware that utilizes a software stack that opportunistically adapts to a sensed or modeled hardware. The envisioned underdesigned and opportunistic computing (UnO) machines face a number of challenges related to the sensing infrastructure and software interfaces that can effectively utilize the sensory data. In this paper, we outline specific sensing mechanisms that we have developed and their potential use in building UnO machines.

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Section: F Variability Simulation Challengesmentioning

confidence: 99%

Section: B Software Adaptations For Quality-complexity Tradeoffsmentioning

confidence: 99%

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Gupta

Agarwal

Dolecek

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

138

116

View full text Add to dashboard Cite

show abstract

“…2, [60] explored a variability-aware duty cycle scheduler where application modules specify a range of acceptable duty cycling ratios, and the scheduler selects the actual duty cycle based on run-time monitoring of operational parameters, and a powertemperature model that is learned off-line for the specific processor instance. In context of erroneous UnO machines, several alternatives exist ranging from detecting and then correcting faults within the application as they arise (e.g., [23,25]) to designing applications to be inherently error-tolerant (e.g., application robustification [55]). …”

Section: B Variability-aware Softwarementioning

confidence: 99%

Variability-aware memory management for nanoscale computing

Dutt

Gupta

Nicolau

et al. 2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-As the semiconductor industry continues to push the limits of sub-micron technology, the ITRS expects hardware (e.g., die-to-die, wafer-to-wafer, and chip-to-chip) variations to continue increasing over the next few decades. As a result, it is imperative for designers to build variation-aware software stacks that may adapt and opportunistically exploit said variations to increase system performance/responsiveness as well as minimize power consumption. The memory subsystem is one of the largest components in today's computing system, a main contributor to the overall power consumption of the system, and therefore one of the most vulnerable components to the effects of variations (e.g., power). This paper discusses the concept of variability-aware memory management for nanoscale computing systems. We show how to opportunistically exploit the hardware variations in onchip and off-chip memory at the system level through the deployment of variation-aware software stacks.

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“…Alternatively, separate processors can be employed to ensure correctness or enhance performance [7,8]. Other techniques, such as those described in [6] and [13], allow the propagation of errors up to the software, where they can either be ignored if the application is robust enough, or corrected through software error correction.…”

Section: Error Resiliency Techniquesmentioning

confidence: 99%

Optimal power/performance pipelining for error resilient processors

Zea

Sartori

Ahrens

et al. 2010

2010 IEEE International Conference on Computer Design

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Timing speculation has been proposed as a technique for maximizing energy efficiency of processors with minimal loss in performance. A typical implementation of timing speculation involves relaxing the timing constraints of a processor to a point where errors are possible but rare, and employing an error recovery mechanism to ensure correct functionality. This allows significant energy efficiency gains with a small recovery overhead.Previous work on timing speculation has either explored the benefits of customizing the design methodology for a particular error resilience mechanism or attempted to understand the benefits from error resilience for a particular resiliency mechanism. There is no work, to the best of our knowledge, that attempts to understand the benefits of co-optimizing microarchitecture and error resilience.In this thesis, we present the first study on co-optimizing a processor pipeline and an error resilience mechanism. We develop an analytical model that relates the benefits from error resiliency to the depth of the pipeline as well as its circuit structure. The model is then used to determine the optimal pipeline depth for different energy efficiency metrics for different error resilience overheads. Our results demonstrate that several interesting relationships exist between error resilience and pipeline structure. For example, we show that there are significant energy efficiency benefits to pipelining an architecture for an error resiliency mechanism versus error resiliency-agnostic pipelining. As another example, we show that benefits from error resiliency are greater for short pipelines than long pipelines. We also confirm that the benefits from error resiliency are higher when the circuit structure is such that the error rate increases slowly on reducing input voltage versus a circuit optimized for power where a slack wall exists at the nominal operating point. We quantify the difference in benefits from error resiliency for irregular versus ii regular workloads and show that benefits from error resiliency are higher for irregular workloads. Finally, we discuss the relationship between frequency and voltage-based timing speculation schemes, and draw conclusions about when is best to employ each. Our analytical results were validated using a cycle-accurate simulation-based model.iii

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A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance

Cited by 37 publications

References 15 publications

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Variability-aware memory management for nanoscale computing

Optimal power/performance pipelining for error resilient processors

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