A parallel ADC for high-speed CMOS image processing system with 3D structure

Kiyoyama, K.; Ohara, Yuki; Kw, Lee; Yang, Young-Joon; Fukushima, T.; Tanaka, Tetsu; Koyanagi, Mitsumasa

doi:10.1109/3dic.2009.5306583

Cited by 17 publications

(3 citation statements)

References 6 publications

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“…3-D stacked multicore processors are used to process the very large amount of data provided from a pair of 3-D stacked CIS chips with high speed and low power. 30,31) Parallel processing is indispensable to achieve high speed and low power operation in multicore processors. The 3-D stacked structure is necessary for the high performance parallel processing.…”

Section: -D Stacked Image Sensor System For Autonomous Driving Assistmentioning

confidence: 99%

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

Lee¹

2015

Journal of the Microelectronics and Packaging Society

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Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore`s law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

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Section: -D Stacked Image Sensor System For Autonomous Driving Assistmentioning

confidence: 99%

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

Lee¹

2015

Journal of the Microelectronics and Packaging Society

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“…In 3D mixed-signal integration systems, analog circuits, digital circuits and sensors are usually vertically stacked. Kiyoyama et al [13] has proposed a 3D stacked image processing system, in which, a parallel analog digital convertor (ADC) with hierarchical correlated double sampling technique is vertically stacked with image processing circuit by TSVs. Liu et al [14] reports the design of a TSV based three-layer stacked 12-bit successive approximation register (SAR) ADC, where the analog parts of ADC are stacked on top of digital parts.…”

Section: Introductionmentioning

confidence: 99%

Modeling and analysis of vertical noise coupling in TSV-based 3D mixed-signal integration

Wang

Ding

Chen

et al. 2016

Microelectronic Engineering

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This paper reports on modeling and analysis of vertical noise coupling between adjacent chips in TSVs-based 3D mixed-signal integration. The coupling between clock channel in digital IC and channel routing wires (CRWs) in analog IC is studied in both frequency domain and time domain. According to physical architecture, a broadband equivalent circuit model of vertical noise coupling is proposed. The comparison of S parameters from full-wave electromagnetic (EM) simulation and circuit model shows a good agreement. The coupling mechanism is discussed from transfer impedance between clock channel and CRWs. The impacts of design variables (such as geometry dimension, 3D stacking process, layout floorplan) on noise coupling are investigated. Four approaches are proposed to reduce the vertical noise coupling and compared with the baseline model. Finally, the time domain analysis shows that the rising/falling time determines peak-to-peak noise voltage and the far-end exhibits larger noise than the near-end.

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“…However, a number of MOSFETs are required for each pixel, and it is difficult to simultaneously satisfy both requirements of high-sensitivity and high-resolution for the image sensor. To realize a CMOS image sensor with highspeed, high-sensitivity, and high-resolution, we have proposed a block-parallel image processing system with 3-D stacked structure [5][6][7]. Our eventual target is to achieve parallel A/D conversion and digital readout at a frame rate of 10000 frames/s with a pixel number of 2-MPixel.…”

Section: Introductionmentioning

confidence: 99%

A block-parallel signal processing system for CMOS image sensor with three-dimensional structure

Kiyoyama

Fukushima

et al. 2010

2010 IEEE International 3D Systems Integration Conference (3DIC)

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In this paper, we describe the fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling (CDS) array, and analog-to-digital converter (ADC) array. To realize high-speed image capturing sensor, we have proposed a blockparallel signal processing with three-dimensional (3-D) structure.In proposed system, one block consists of 3 stacked layers which are 100 pixels image sensor, CDS circuit, and one ADC. Each circuit layer is vertically stacked and electrically connected by through-Si vias (TSVs), which can improve sensor performance. On the other hand, the block-parallel system requires ADC with extremely low-power and small circuit area, ADC is required. Therefore, the trade-off among area, power dissipation and conversion speed is important factor, and critical challenge. ADC designed in the test chip for functional evaluation employed the time interleaved charge-redistribution successive approximation (SAR) method. The proposed 9-bit ADC was designed in 90-nm CMOS technology, and achieved power dissipation less than 0.5mW with supply voltage of 1.0V and 4 MS/s conversion rate. The circuit area is 100 ×100 ȝm 2 .

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A parallel ADC for high-speed CMOS image processing system with 3D structure

Cited by 17 publications

References 6 publications

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

Modeling and analysis of vertical noise coupling in TSV-based 3D mixed-signal integration

A block-parallel signal processing system for CMOS image sensor with three-dimensional structure

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