A Parallel Bitstream Generator for Stochastic Computing

Wang

2019 International Conference on IC Design and Technology (ICICDT)

et al. 2019

Self Cite

Convolutional neural network (CNN) achieves excellent performance on fascinating tasks such as image recognition and natural language processing at the cost of high power consumption. Stochastic computing (SC) is an attractive paradigm implemented in low power applications which performs arithmetic operations with simple logic and low hardware cost. However, conventional memory structure designed and optimized for binary computing leads to extra data conversion costs, which significantly decreases the energy efficiency. Therefore, a new memory system designed for SC-based multiply-accumulate (MAC) engine applied in CNN which is compatible with conventional memory system is proposed in this paper. As a result, the overall energy consumption of our new computing structure is 0.91pJ, which is reduced by 82.1% compared with the conventional structure, and the energy efficiency achieves 164.8 TOPS/W. I.

Section: A Stochastic Computing (Sc)mentioning

confidence: 99%

“…Both of them take up a large proportion in the overall power consumption. Therefore, works on low power converters [12] and new computing structure with simple conversion procedures are of great importance.…”

Section: A Stochastic Computing (Sc)mentioning

confidence: 99%

Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing

Wang

2019 International Conference on IC Design and Technology (ICICDT)

et al. 2019

Self Cite

“…We can observe that every bit of N1 sees every bit of N2, so that the calculation result will be completely accurate. Moreover, binary number can be converted into deterministic code with simple decoder in parallel [9], which highly improves the energy efficiency and reduces the computing latency.…”

Section: Background and Motivation 21 Backgroundmentioning

confidence: 99%

An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing

2019 IEEE 13th International Conference on ASIC (ASICON)

Song

Wang

et al. 2019

Self Cite

Convolutional neural networks (CNN) have achieved excellent performance on various tasks, but deploying CNN to edge is constrained by the high energy consumption of convolution operation. Stochastic computing (SC) is an attractive paradigm which performs arithmetic operations with simple logic gates and low hardware cost. This paper presents an energy-efficient mixed-signal multiply-accumulate (MAC) engine based on SC. A parallel architecture is adopted in this work to solve the latency problem of SC. The simulation results show that the overall energy consumption of our design is 5.03pJ per 26-input MAC operation under 28nm CMOS technology.

“…However, SC requires a stochastic sequence including a large number of '0' s and '1' s [8], and generating the long stochastic sequence results in latency issues [9,10]. For instance, in 8-bit computation, the SC requires a 256-bit-long stochastic sequence [8].…”

Section: Introductionmentioning

confidence: 99%

Parallel Stochastic Computing Architecture for Computationally Intensive Applications

Kim

Jeong

et al. 2023

Electronics

Stochastic computing requires random number generators to generate stochastic sequences that represent probability values. In the case of an 8-bit operation, a 256-bit length of a stochastic sequence is required, which results in latency issues. In this paper, a stochastic computing architecture is proposed to address the latency issue by employing parallel linear feedback shift registers (LFSRs). The proposed architecture reduces the latency in the stochastic sequence generation process without losing accuracy. In addition, the proposed architecture achieves area efficiency by reducing 69% of flip-flops and 70.4% of LUTs compared to architecture employing shared LFSRs, and 74% of flip-flops and 58% of LUTs compared to the architecture applying multiple LFSRs with the same computational time.