A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells

Casotto, A.; Romeo, F.; Sangiovanni‐Vincentelli, Alberto

doi:10.1109/tcad.1987.1270327

Cited by 152 publications

(50 citation statements)

References 7 publications

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“…There are already several placement tools implemented using simulated annealing [170,171,172,173,95]. Integrating placement into the framework would give the benefit of an even more complex objective function, considering technology parameters regarding area, delay, placeability, routability, power consumption, etc.…”

Section: Open Problemsmentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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Section: Open Problemsmentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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“…Speedups of 12 on 16 processors were reported. Casotto et al [15] worked on speeding up simulated annealing for the placement of macrocells, and achieved speedups of 6 using 8 processors using this approach on a shared memory multiprocessor. Sun and Sechen [16] have shown results achieving near linear speedup on a network of workstations, also using this approach.…”

Section: Parallel Movesmentioning

confidence: 99%

Exploring Asynchronous MMC-Based Parallel SA Schemes for Multiobjective Cell Placement on a Cluster of Workstations

et al. 2011

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Simulated Annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinatorial optimization problems. However, depending on the size of the problem, it may have large run-time requirements. One practical approach to speed up its execution is to parallelize it. In this paper, several parallel SA schemes based on the Asynchronous Multiple-Markov Chain model are explored. We investigate the speedup and solution quality characteristics of each scheme when implemented on an inexpensive cluster of workstations for solving a multi-objective cell placement problem. This problem requires the optimization of conflicting objectives (interconnect wire-length, power dissipation, and timing performance), and Fuzzy logic is used to integrate the costs of these objectives. Our goal is to develop several AMMC based parallel SA schemes and explore their suitability for different objectives: achieving near linear speedups while still meeting solution quality targets, and obtaining higher quality solutions in the least possible duration.

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“…An approach that is application independent and allows the exploitation of a reasonable amount of parallelism is to generate and evaluate several moves simultaneously 2, 3,4,6,14,18,19,21,24,26]. Since computing E requires global state information, processors manipulating the state simultaneously may interfere with each other.…”

Section: Parallel Simulated Annealing With Simultaneous Movesmentioning

confidence: 99%

Trading accuracy for speed in parallel simulated annealing with simultaneous moves

Durand

White

2000

Parallel Computing

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A common approach to parallelizing simulated annealing to generate several perturbations to the current s o l u t i o n s i m ultaneously, requiring synchronization to guarantee correct evaluation of the cost function. The cost of this synchronization may be reduced by allowing inaccuracies in the cost calculations. We provide a framework for understanding the theoretical implications of this approach based on a model of processor interaction under reduced synchronization that demonstrates how errors in cost calculations occur and how to estimate them. We show h o w bounds on error in the cost calculations in a s i m ulated annealing algorithm can be translated into worst-case bounds on perturbations in the parameters which describe the behavior of the algorithm.Keywords: Parallel simulated annealing Metropolis algorithm Boltzmann distribution.Simulated annealing (SA) is an iterative method for nding approximate solutions to intractable combinatorial optimization problems. For parallel implementations of SA based on simultaneous moves, synchronization is a bottleneck because it reduces the amount of available parallelism and increases the overhead. Synchronization costs can be reduced by allowing processors to use out-ofdate state information to evaluate the quality o f i n termediate solutions at the expense of introducing errors into the evaluation function. This approach assumes that SA will still generate a good solution if the size of the errors is controlled.Since 1986, parallel implementations of SA using simultaneous moves have been reported in the literature, using many di erent heuristics to control the size of the error. However, to our knowledge, very little has been published that analyzes the nature and impact of these errors theoretically. In this paper, we model the error that occurs on multiprocessors and analyze this error using techniques from statistical physics. First, a formal model of parallel simulated annealing (PSA) based on simultaneous moves with reduced synchronization is introduced. We describe how e r r o r i n t h e c hange in energy occurs in this model and discuss implementation issues that a ect its size. The e ect of such error on the behavior of SA can be understood through its impact on the frequency with which the algorithm visits states in the solution space. We prove a theorem that

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A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells

Cited by 152 publications

References 7 publications

Integrated logic synthesis using simulated annealing

Integrated logic synthesis using simulated annealing

Exploring Asynchronous MMC-Based Parallel SA Schemes for Multiobjective Cell Placement on a Cluster of Workstations

Trading accuracy for speed in parallel simulated annealing with simultaneous moves

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