A Parallel Simulated Annealing Approach for Floorplanning in VLSI

Fang, Jyh-Perng; Chang, Yang-Lang; Chen, Chih-Chia; Liang, Wen-Yew; Hsieh, Tung-Ju; Satria, Muhammad T.; Han, Chin‐Chuan

doi:10.1007/978-3-642-03095-6_29

Cited by 5 publications

(2 citation statements)

References 15 publications

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“…In this work, another dimension of SA algorithm is devised to find the near optimal solution with primary objective of minimization of wirelength. Simulated Annealing Algorithm [5,6,12,[24][25][26]30] is found to be more simple in computing when compared to GA and PSO techniques and researchers have proved it. SA is an optimizing methodology that accepts solutions with non-zero probability that is tolerant to inferior (uphill) solutions and accepts them.…”

Section: Constraints Of Floorplanmentioning

confidence: 99%

Modified SA algorithm for wirelength minimization in VLSI circuits

Laudis¹,

Anand²,

Sinha

2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

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In modern VLSI circuits, number of parameters viz, placement of components, dead space (un occupied space in the layout) , wire length has to be minimized. The defined problems are non deterministic and NP hard optimization problem. Hence probabilistic (stochastic) methods are adopted to solve these problems. The minimization problems are multi objective optimization problems (MOO). Hence, for the convenience of computation, these MOO problems are converted into Single objective optimization (SOO) problems.It is observed from the previous research works that the bio-inspired algorithms have worked very well in the minimizing process. Evolutionary Algorithms, Genetic Algorithms, Memetic Algorithms were notable in solving the non deterministic hard problems. Moreover, Simulated annealing algorithm developed by Kirpatrick et.al, proved itself to be worthy in the minimization process. The major aim of this research work is to modify or customize the Simulated Annealing Algorithm (SAA) based on the user defined values and test it with various bench marks. This research work may be used to minimize the wire length between the blocks in complex VLSI problems. The capability of the proposed algorithm may be more efficient because of the mechanism of reducing the uphill moves made during the initial stage of the algorithm, extended search at each temperature and the improved neighborhood procedure.

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Section: Constraints Of Floorplanmentioning

confidence: 99%

Modified SA algorithm for wirelength minimization in VLSI circuits

Laudis¹,

Anand²,

Sinha

2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

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“…al. (2009) [17] adopted a parallel computing environment to increase the throughput of solution space searching in order to deal with the floorplan design with enormous amount of interconnections and design blocks. S. Anand , S. Saravanasankar (2010) [18] the aim of their work was to minimize the unused area, that is, dead space in the floorplan, in addition to these objectives.…”

Section: Simulated Annealing (Sa)mentioning

confidence: 99%

Different Methodologies to Solve Vlsi Floorplanning Problem

Jain,

Singh

2022

YMER

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Due to the exponential increase in number of components on a VLSI (Very Large-Scale Integration) chip over the years, there is a need to develop automated algorithms to decide the relative positions of circuits on a chip. In order to improve the performance of a chip, it is essential to deal with multiple objectives including area and wire length during the floor planning phase. Modern very large-scale integration technology is based on fixed-outline floorplan constraints, generally with an objective of minimizing area and wirelength between the modules. This survey paper gives an up-to-date account on various approaches used to solve VLSI floor planning problem. Keywords—Genetic algorithm, Non-slicing floorplan, Soft modules, VLSI floor planning.

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VLSI Floorplanning Using Entropy Based Intelligent Genetic Algorithm

Singh

Jain²

2018

Communications in Computer and Information Science

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A Parallel Simulated Annealing Approach for Floorplanning in VLSI

Cited by 5 publications

References 15 publications

Modified SA algorithm for wirelength minimization in VLSI circuits

Modified SA algorithm for wirelength minimization in VLSI circuits

Different Methodologies to Solve Vlsi Floorplanning Problem

VLSI Floorplanning Using Entropy Based Intelligent Genetic Algorithm

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