A parallel VLSI architecture for Markov chain Monte Carlo based MIMO detection

Abstract

Multiple-input multiple-output (MIMO) wireless transmission together with iterative decoding at the receiver is a key technique to achieve high spectral efficiency. However, particularly the required soft-input soft-output (SISO) MIMO detector entails a very high complexity, which motivates the investigation of suboptimal detectors with reduced complexity. In this paper, we present-to the best of our knowledgethe first implementation of a parallel VLSI architecture for a SISO detector based on Markov chain Monte Carlo (MCMC) methods. The proposed architecture is scalable and allows to exploit the parallelism inherent in the considered MCMC algorithm. We investigate the implementation costs and show that this architecture covers a wide range of trade-offs between throughput and silicon area.

VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers

“…Its basic idea is to recursively compute the metric in Eq. (1) by tracking the changes while drawing bits [1]. First, we introduce the basic concepts required for understanding the algorithm, then describe the algorithm in detail.…”

“…First, we introduce the basic concepts required for understanding the algorithm, then describe the algorithm in detail. For the theoretic background, the reader is kindly referred to [1], [2].…”

“…Related Work: The only MCMC-based SISO MIMO detector ASIC design truly supporting independent parallel Gibbs Samplers to date is presented in [1]. Amongst other things, [1] introduces an initialization scheme for the completely recursive, and thus simplified, computation of the detector states, and shows how to reuse the circuitry to draw independent first samples.…”

“…Amongst other things, [1] introduces an initialization scheme for the completely recursive, and thus simplified, computation of the detector states, and shows how to reuse the circuitry to draw independent first samples. However, a multiplier in the timing critical path yields a limited throughput and a relatively large area consumption.…”

“…Contribution: We present a complete redesign of the MCMC-based MIMO detector architecture presented in [1], with multiplier-free Gibbs Samplers and further architectural improvements that result in a significant area reduction and timing improvement. Post-layout area and clock period reduce by about 50% and 40% respectively.…”