A Paralleled SiC MOSFET Half-bridge Unit With Distributed Arrangement of DC Capacitors

Qu, Jianzhen; Yu, Yifan; Zhang, Qianfan; Cui, Shumei

doi:10.1109/iciea48937.2020.9248117

Cited by 2 publications

(3 citation statements)

References 28 publications

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“…The design details of the paralleled SiC MOSFET halfbridge unit that used in the multiplexing converter, as shown in Fig. 3(a), was already given in [40], where eight discrete SiC MOSFETs are used with the distributed arrangement of dc capacitors. In this section, the parasitic CM capacitances of the paralleled unit are analyzed and compared with the measurements.…”

Section: A Parasitic CM Capacitors Of the Paralleled Sic Mosfet Half-bridge Unitmentioning

confidence: 99%

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Conducted EMI Investigation of a SiC-Based Multiplexing Converter for EV/PHEV

Zhang

Wang

et al. 2021

IEEE Access

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This paper investigates the conducted electromagnetic interference (EMI) characteristics of an on-board multiplexing converter that utilizes paralleled silicon carbide (SiC) devices to achieve high efficiency and high-power density for the application in electric vehicles (EVs) and plug-in hybrid electric vehicles (PHEVs). The multiplexing converter can operate as a three-phase interleaved DC/DC converter with a peak output power of 60 kW or an integrated two-stage non-isolated on-board charger (OBC) with an output power of 6.6 kW. The novelty of this paper is that it reveals that in the DC/DC mode the series resonance between the input negative lead parasitic inductance and the high frequency transmission line effects of the input power inductor will increase the conducted EMI levels, which can be mitigated by optimizing the winding methods of the power inductor or by adding a small capacitor, and reveals that in the non-isolated OBC mode the shielded cable on the battery-side will increase the grid-side EMI in the low frequency ranges, which can be suppressed by integrated installation of EMI filters without affecting the system power density. Firstly, parasitic parameters of the components of the multiplexing converter, such as the power inductors, the SiC MOSFETs and the shielded cables, are extracted and validated with impedance measurements, and the corresponding equivalent circuit models are established. Then, the conducted EMI simulation models of the multiplexing converter in different working modes are established. The influence of different interference sources and different parasitic parameters on the system EMI characteristics are analyzed, and the effective EMI suppression measures are given without affecting the system power density. Finally, the conducted EMI characteristics of the multiplexing converter and the effectiveness of the proposed EMI suppression measures are tested and verified through experiments.INDEX TERMS Common mode (CM), electromagnetic interference (EMI), EMI modeling, EMI reduction, EMI simulation, parasitic parameters, silicon carbide (SiC) MOSFET.

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Section: A Parasitic CM Capacitors Of the Paralleled Sic Mosfet Half-bridge Unitmentioning

confidence: 99%

“…The PCB layout is exported to the Q3D as shown in Fig. 8(a) to extract the parasitic parameters, which has been discussed detailly in [40]. The layer stack-up of the power layout is shown in Fig.…”

Section: E Parasitic Parameters Of the Pcb Layoutmentioning

confidence: 99%

Conducted EMI Investigation of a SiC-Based Multiplexing Converter for EV/PHEV

Zhang

Wang

et al. 2021

IEEE Access

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“…Fig.4(a) shows the block diagram to determine the pulse widths and deadtimes of gate signals2 . In addition to the duty cycle D, the dc-bus voltage V dc and the average load current I Lo are required in (41), (43) and(29) to determine the initial conditions I Lo,T 0 , I La,T 0 and I Lm,T 5 .…”

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Enabling Resonant Commutated Pole in Parallel Power FET Bridge Legs

Shen

Jiang

Zhao

et al. 2021

IEEE Trans. Power Electron.

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To meet the requirements of higher current ratings and lower thermal impedances, paralleling power field-effect transistor (FET) discretes or modules is often a cost-effective or even an unavoidable solution. While paralleling FETs allows for a significant reduction in conduction loss, the switching loss is increased in hard switching applications. This paper proposes a generic soft-switching modulation scheme for parallel power FET bridge legs. Part of the paralleled FET legs is chosen as an auxiliary leg that is turned ON prior to the remaining main legs. A resonant commutated pole (RCP) mode is then created, which enables the high-side FET of the auxiliary leg to achieve zero-current switching (ZCS) or quasi-ZCS, and the remaining FETs to achieve zero-voltage switching (ZVS). Thus, we can significantly reduce the switching loss that normally dominates the total power loss of high-frequency hard-switching converters particularly at partial and light loads. Experimental results from three parallel GaN high-electron-mobility transistor (HEMT 1 ) legs validate the effectiveness of this RCP-enabled solution in reducing switching losses and improving power conversion efficiencies. This paper is accompanied by supplementary JIF and PDF files demonstrating the operational details of the RCP mode. Index Terms-Parallel power FETs, zero-voltage switching (ZVS), zero-current switching (ZCS), resonant commutated pole (RCP)

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A Paralleled SiC MOSFET Half-bridge Unit With Distributed Arrangement of DC Capacitors

Cited by 2 publications

References 28 publications

Conducted EMI Investigation of a SiC-Based Multiplexing Converter for EV/PHEV

Conducted EMI Investigation of a SiC-Based Multiplexing Converter for EV/PHEV

Enabling Resonant Commutated Pole in Parallel Power FET Bridge Legs

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