A parameterized floating-point exponential function for FPGAs

Abstract

Abstract-This article presents a generator of floating-point exponential operators targeting recent FPGAs with embedded memories and DSP blocks. A single-precision operator consumes just one DSP block, 18Kbits of dual-port memory, and 392 slices on Virtex-4. For larger precisions, a generic approach based on polynomial approximation is used and proves more resourceefficient than the literature. For instance a double-precision operator consumes 5 BlockRAM and 12 DSP48 blocks on Virtex-5, or 10 M9k and 22 18x18 multipliers on Stratix III. This approach is flexible and is demonstrated to scale up to quadrupleprecision, while enabling frequencies close to the FPGA's nominal frequency. All the proposed architectures are last-bit accurate for all the floating-point range. They are available in the open-source FloPoCo framework.

Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs

“…Since the NFG directly realizes the function table of a floating-point function using a piecewise-split EVMDD, it is more accurate than existing NFGs using polynomial approximation [2,3,6,20,24].…”

“…However, floating-point representation tends to produce complex and slow NFGs. Thus, the design of floating-point NFGs is especially hard, and only design methods for some numeric functions are known [2,3,6,20,24]. Since these design methods are intended only for specific functions, different functions need different design methods and architectures.…”

Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions

“…3. Since the proposed NFG directly realizes the function table of a floating-point function using an EVMDD, it is more accurate than existing NFGs using polynomial approximation [4,5,8,22,26]. 4.…”

“…However, floating-point representation tends to produce complex and slow NFGs. Thus, the design of floating-point NFGs is especially hard, and only design methods for some elementary functions are known [4,5,8,22,26]. Since these design methods are intended only for specific functions, different functions need different design methods and architecturers.…”

Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables

“…De plus, il sera possible de le tailler au plus juste pour l'application. Le présent article, qui reprend et étend des publications précédentes (Detrey et al, 2005c ;Detrey et al, 2005b ;Detrey et al, 2006), montre que cette flexibilité du FPGA lui permet alors de surpasser en débit l'implé-mentation dans le processeur. Pour la simple précision, on peut ainsi obtenir un débit dix fois plus élevé, là où les opérateurs de base avaient un débit dix fois plus faible.…”