A pattern-guided adaptive equalizer in 65nm CMOS

Abstract

The use of adaptive equalizers at the front end of receivers is becoming a necessity as the data rates increase without channel improvements. Adaptive equalizers can be implemented using data-aided or non-data-aided schemes [1], with the latter requiring less area and power. Previous non-data-aided adaptive schemes [2][3] implement an asynchronous analog algorithm where the power spectrum of the received signal is checked for balance around a threshold frequency. Similarly, [4] proposes a digital adaptive algorithm which is based on the detection of specific 5-bit patterns. In all three works [2][3][4], however, adaptation is provided only for equalizers with a single coefficient, which are suitable for well-behaved channels. In contrast, this paper presents a digital adaptive engine for an equalizer with two coefficients: one adjusting the equalizer gain at the Nyquist frequency (f N ) and one at f N /2. Furthermore, the proposed engine is asynchronous; it can function when driven by a blind clock at the receiver. This is useful as it allows the adaptation process to start even when the CDR has not yet achieved lock. This also avoids a deadlock situation where the CDR and equalizer require simultaneous access to the equalized data and the recovered clock. Our measured results of the proposed adaptive equalizer in 65nm CMOS confirm that the adaptation converges to within 2.6% of the optimal vertical eye opening in less than 400µs for two different channels at a data rate of 6Gb/s with a 25,000ppm frequency offset.Figure 20.5.1 illustrates the concept behind the proposed adaptive equalizer. We assume an equalizer with controllable gains at f N (C1) and f N /2 (C2) to compensate for the channel loss at f N and f N /2, respectively. To control the equalizer gain at f N , we count the number of 4-bit patterns whose signal power is concentrated around f N (and have no signal power at f N /2). It can be shown that the two 4-bit patterns that have this property are 0101 and 1010. We refer to these patterns as Type 1. Similarly, to control the gain at f N /2, we count the number of 4-bit patterns whose signal power is concentrated around f N /2 (and have no power at f N ). There are four 4-bit patterns among the possible 16 that have this property. We refer to these patterns as Type 2. It can be shown that the remaining ten 4-bit patterns have identical signal power at f N and f N /2. These patterns are not utilized in the proposed equalization scheme.As shown in Fig. 20.5.2, the incoming data is attenuated by the channel and subsequently boosted by the equalizer with two independent, adjustable gains, C1 and C2. The equalized signal is sampled by two slicers (S1 and S2) whose thresholds differ by ΔV (mV). If the signal amplitude is above ΔV (mV), the outputs of S1 and S2 will be identical, signifying a vertical eye opening larger than ΔV (mV). The adaptive controller adjusts C1 and C2 to equalize the vertical eye opening to ΔV for both Type 1 and Type 2 patterns. This is achieved by counting each pattern at the output ...

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