A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs

Maes, Roel; Schellekens, Dries; Verbauwhede, Ingrid

doi:10.1109/tifs.2011.2169667

Cited by 62 publications

(58 citation statements)

References 24 publications

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“…In this paper, we evaluate the practical feasibility of their scheme. As already partly indicated by the authors of [9], the proposed architecture is vulnerable for side-channel attacks. Additionally, commercially available tools do not allow nested and flexible placement of IP cores.…”

Section: Introduction and Previous Workmentioning

confidence: 75%

“…Simpson and Schaumont describe an off-line authentication scheme for embedded software IP modules in FPGAs [16]. Besides this software-oriented approach, a number of hardware solutions were proposed [5][6][7]9]. In [6], a proof-of-concept implementation is presented to reconfigure the majority of the FPGA such that it has a design, containing a specific IP core.…”

Section: Introduction and Previous Workmentioning

confidence: 99%

“…However, this does not provide a flexible way of obtaining and implementing one or more IP cores. Although none of the other solutions [5,7,9] were implemented in practice, the work of Maes et al [9] elaborates the most on practical issues. Moreover, their work offers the pay-per-use feature where the system developer pays a price for the IP core per device in which it is instantiated.…”

Section: Introduction and Previous Workmentioning

confidence: 99%

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Practical feasibility evaluation and improvement of a pay-per-use licensing scheme for hardware IP cores in Xilinx FPGAs

et al. 2014

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In earlier published work, Maes et al. present a pay-per-use licensing scheme for hardware Intellectual Property (IP) cores. This scheme focuses on the use of IP cores on static random access memory-based field programmable gate arrays (FPGAs) and is mainly based on the partial reconfigurability property of this type of FPGA. Our work evaluates the practical feasibility of the scheme and the accompanying architecture. As already (partly) indicated by Maes et al., their solution introduces some security and usability issues. Therefore, we present improvements to the scheme and the architecture together with an additional method for decreasing the area overhead. The overall result is the first practical implementation of the pay-per-use licensing scheme occupying 841 slices on a Xilinx XC6S-LX45 FPGA. The small area overhead is mainly achieved by moving the storage of keys from slice flip-flops to configuration memory. Moreover, the implementation would not have been feasible with commercially available tools. We use an academic tool that allows nested partial reconfiguration and flexible IP core placement.

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Section: Introduction and Previous Workmentioning

confidence: 75%

Section: Introduction and Previous Workmentioning

confidence: 99%

Section: Introduction and Previous Workmentioning

confidence: 99%

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Practical feasibility evaluation and improvement of a pay-per-use licensing scheme for hardware IP cores in Xilinx FPGAs

et al. 2014

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“…(2) Charging for the use of the IP core is proportional to the sale of the system developed, reducing the stake of the system developer in the relentless market competition. With these advantages, the pay-peruse model becomes the common target of almost all the latter methods [38,[40][41][42][43][44]. The details of the scheme are described below.…”

Section: Pay-per-use Based Fpga Ip Licensing Schemementioning

confidence: 99%

“…Later, a scheme [41] that is applicable to commercially available FPGA devices is created without incurring any hardware modification. Instead of assuming that the FV is fully trusted by other parties in the market, the scheme separates the role of the FV and the TTP.…”

Section: Trusted Third Party With Symmetric-key Crypto Based Key Derimentioning

confidence: 99%

Secure Licensing of IP Cores on SRAM-Based FPGAs

Zhang

Chang

2016

Secure System Design and Trustable Computing

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The rapid increase in FPGA devices' capacity has enabled the implementation of complete sophisticated systems. The widening design productivity gap and shrinking time-to-market window have made licensing of external IP cores for system development pervade. The upfront IP licensing model currently used in the market is not a good fit to the FPGA IP market as the blanket IP license fee is too expensive for the majority of FPGA-based system developers who target low-to-medium volume applications. This chapter presents a detailed discussion on secure licensing of the IP cores that is more suitable for FPGA IP market. After the background information such as the stakeholders in the market, common attacks to the IP cores and desiderata for an effective licensing scheme have been presented, two categories of IP licensing schemes, i.e., those that employ only the conventional crypto primitives and those that exploit the emerging PUF primitive, are detailed and illustrated. The shared target of these schemes is to realize a secure pay-per-use licensing model where the system developer is proportionally charged for the use of the IP core. Along with the discussion of the schemes, some noteworthy features are also highlighted such as the authenticity of the IP core as well as the fault tolerance, tamper and side-channel resistance of the employed hardware primitives. The aim of this chapter is to provide a comprehensive overview of existing developments in FPGA IP licensing protocols and facilitate the development of new schemes that are more efficient and costeffective.

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