A performance analysis of pulse stream neural and fuzzy computing systems

IEICE Trans. Inf. & Syst.

2015

SUMMARYNeural networks are widely used in various fields due to their superior learning abilities. This paper proposes a hardware winnertake-all neural network (WTANN) that employs a new winner-take-all (WTA) circuit with phase-modulated pulse signals and digital phase-locked loops (DPLLs). The system uses DPLL as a computing element, so all input values are expressed by phases of rectangular signals. The proposed WTA circuit employs a simple winner search circuit. The proposed WTANN architecture is described by very high speed integrated circuit (VHSIC) hardware description language (VHDL), and its feasibility was tested and verified through simulations and experiments. Conventional WTA takes a global winner search approach, in which vector distances are collected from all neurons and compared. In contrast, the WTA in the proposed system is carried out locally by a distributed winner search circuit among neurons. Therefore, no global communication channels with a wide bandwidth between the winner search module and each neuron are required. Furthermore, the proposed WTANN can easily extend the system scale, merely by increasing the number of neurons. The circuit size and speed were then evaluated by applying the VHDL description to a logic synthesis tool and experiments using a field programmable gate array (FPGA). Vector classifications with WTANN using two kinds of data sets, Iris and Wine, were carried out in VHDL simulations. The results revealed that the proposed WTANN achieved valid learning. key words: neural network, winner-take-all, supervised learning, digital phase-locked loop, hardware architecture

Section: Introductionmentioning

confidence: 99%

Scalable Hardware Winner-Take-All Neural Network with DPLL

Azuma

IEICE Trans. Inf. & Syst.

2015

“…One of the effective approaches for hardware implementation of neural networks is a pulse stream-based architecture [1][2][3][4][5][6][7]. In synchronous pulse neural networks, the signal level is represented by pulse density which is normalized so that the maximum pulse frequency f MAX is 1.0.…”

Section: Introductionmentioning

confidence: 99%

A multilayer neural network with pulse position modulation

Systems & Computers in Japan

2003

SUMMARYThe problem of the pulse mode neural network is that the synapse weight is bounded between +1 and -1. In order to enhance the weight range, this paper proposes a new weighting method that is a combination of pulse density modulation and pulse position modulation (PPM). The feasibility of the proposed method is verified by experimental MNN with on-chip learning. A modified back-propagation algorithm is used for the on-chip learning. The experimental results show that the proposed MNN architecture has the ability to handle high-resolution classifying problems and good on-chip learning capability.

“…The stochastic computing is executed by basic logic gates with random pulse sequences, for example, a multiplication is performed with a single AND gate. However, the drawback of the conventional pulse-mode neural network is that the activation function provided by the pulsed nonlinearity is almost fixed and the accuracy of the pulse mode computing is inferior to that of fully digital arithmetic operation [7].…”

Section: Introductionmentioning

confidence: 99%

Multilayer neural network with on-chip learning based on frequency-modulated pulse signals and voting neurons

Electron. Comm. Jpn. Pt. III

2000

In this paper, a pulse‐mode multilayer neural network with on‐chip learning is proposed. The neuron unit uses voting circuit as a nonlinear adder to improve the nonlinear activation function. Moreover, the voting circuit is modified to have adjustable nonlinear characteristic. As the signal level is expressed by the frequency, synapse multipliers are realized by simple frequency converters. The back propagation algorithm is used for the on‐chip learning. The proposed multilayer neural network is implemented on field programmable gate array (FPGA), and various experiments are conducted. The results show that the proposed neuron has adjustable nonlinear function. The learning capability of the proposed network is also verified by the experiments. © 2000 Scripta Technica, Electron Comm Jpn Pt 3, 84(1): 32–42, 2001