A Perspective on Dark Silicon

Kanduri, Anil; Rahmani, Amir M.; Liljeberg, Pasi; Hemani, Ahmed; Jantsch, Axel; Tenhunen, Hannu

doi:10.1007/978-3-319-31596-6_1

Cited by 23 publications

(11 citation statements)

References 26 publications

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“…4a). Since higher chip densities are being required to match the demands of machine learning, big data and mathematical models, the fraction occupied by "dark silicon" may soon be larger than 90% (Taylor 2012; Kanduri et al 2017) (Fig. 4b).…”

Section: Computational Exhaustionmentioning

confidence: 99%

Mind the hubris: complexity can misfire

Puy¹,

Saltelli²

2022

Preprint

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Section: Computational Exhaustionmentioning

confidence: 99%

Mind the hubris: complexity can misfire

Puy¹,

Saltelli²

2022

Preprint

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show abstract

“…Depending on the behaviour/characteristics of an application, a router from each node is selected and formed into a low power NoC Fabric while idle routers are switched off. 8 EAI Endorsed Transactions on Industrial Networks and Intelligent Systems 06 2018 -09 2018 | Volume 5 | Issue 15| e5…”

Section: Run-time Power Consumption Techniques For Noc Architecturesmentioning

confidence: 99%

“…For decades, Moore and Dennardian theories were the embodiment of exa-scale technology. Dennard's scaling revealed that, by reducing the size of transistors, it can be utilised at lower power and voltage because, power density is equivalent to the square of applied voltage, therefore, it remains the same [6][7][8]. Consequently, by reducing the physical parameters of transistors, it has been possible to utilise them under lower power and voltage.…”

Section: Introductionmentioning

confidence: 99%

“…Unfortunately, transistor size reduction has caused a halt in voltage scaling down and resulted with an increase in the amount of sub-threshold leakage, as well the gate tunnelling leakage current caused by having thinner gate oxides. Therefore, it has been reported that leakage power contributes to a higher percentage of the chip's total power consumption at the deep-sub micron level [8][9][10]. Consequently, high power density generates excess heat and increases the temperature of the chip.…”

Section: Introductionmentioning

confidence: 99%

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A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Ofori-Attah¹,

Wang²,

Agyeman³

2018

EAI Endorsed Transactions on Industrial Networks and Intelligen

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Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with manycore integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

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“…Power densities of may-core systems are increasing due to disproportional voltage and technology node scaling, contributing to higher on-chip temperatures [1], [2]. As a result, a section of the chip has to remain inactive to function within safe thermal limits.…”

Section: Introductionmentioning

confidence: 99%

adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning

Kanduri

Haghbayan

Rahmani

et al. 2018

IEEE Trans. Comput.

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Increasing power densities of many-core systems leaves a fraction of on-chip resources inactive, referred to as dark silicon. Efficient management of critical interlinked parameters-power, performance and temperature can improve resource utilization and mitigate dark silicon. In this paper, we present a run-time resource management system for thermal aware performance boosting using a dark silicon aware run-time application mapping strategy. The mapping policy patterns inactive cores among active cores for relatively lower and even distribution of operating temperatures. This provides enough thermal headroom for boosting the frequency of active cores upon performance surges and allows sustained boosting periods, improving the performance further. We design a controller for thermal aware performance boosting that decides on efficient allocation utilization of power budget and thermal headroom obtained from patterning. Our strategy yields up to 37% better throughput, 29% lower waiting time and up to 2 × longer boosting periods, in comparison with other state-of-the-art run-time mapping policies.

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A Perspective on Dark Silicon

Cited by 23 publications

References 26 publications

Mind the hubris: complexity can misfire

Mind the hubris: complexity can misfire

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning

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