A pFET-access radiation-hardened SRAM for extreme environments

Barlow, M.; Fu, Guang; Hollosi, Brent; Lee, C.; Di, Jia; Alan, M.H.; Schupbach, Marcelo; Berger, Richard W.

doi:10.1109/mwscas.2008.4616825

Cited by 11 publications

(5 citation statements)

References 5 publications

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“…Simulation of circuit's parameters over PVT is carried out in order to survey how the variation has effects performance, stability and power of SRAM. [4] a) Process:…”

Section: Results Of Parameters Simulation Over Pvt Variationsmentioning

confidence: 99%

Design A Synchronous Single-Port Sram 1024x32xMUX4 Using 28NM Technology

Phu¹,

Han²,

Luong³

et al. 2021

IJCDS

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“…Simulation of circuit's parameters over PVT is carried out in order to survey how the variation has effects performance, stability and power of SRAM. [4] a) Process:…”

Section: Results Of Parameters Simulation Over Pvt Variationsmentioning

confidence: 99%

Design A Synchronous Single-Port Sram 1024x32xMUX4 Using 28NM Technology

Phu¹,

Han²,

Luong³

et al. 2021

IJCDS

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“…In addition to deep space electronics applications, cryogenic embedded memories can be used in high-performance computing and fuel-cell electric vehicles, and are a viable choice to support superconducting operation in quantum computing [1]- [4]. Despite some previous explorations focusing on cryogenic memories [1], [2], [4]- [6], there is still the need for a cost-efficient and high-density memory design capable of operating within a cryogenic environment.…”

Section: Introductionmentioning

confidence: 99%

STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications

Garzón¹,

Yavits²,

Teman³

et al. 2023

Preprint

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<p>This work explores non-volatile (NV) embedded memories implemented by spin-transfer torque magnetic random access memories (STT-MRAMs). Our designs are based on state-of-the-art perpendicular magnetic tunnel junctions (MTJs) along with a commercial 65 nm planar CMOS Bulk technology node, both operating at the liquid nitrogen temperature, 77 K. We evaluate the impact of cooling down to 77 K of the STT-MRAMs based on single- and double-barrier MTJ (SMTJ and DMTJ), and DMTJ with the relaxed non-volatility. All NV designs were benchmarked against the six-transistor SRAM (6T-SRAM) baseline. Simulation analysis relies on a 512 kB cache memory operating at 77 K. Overall, results show that the implementation of STT-MRAMs with DMTJ devices, and in particular when using the non-volatility approach by reducing the cross-section area, excel in terms of energy consumption, leading to energy savings for write/read access of about 35%/54%. This saving is obtained while also dissipating less leakage power and requiring a smaller bitcell footprint. Moreover, it presents reduced write latency overhead (as much as 1.9 × lower), at the expense of increased read latency and reduced sensing margins of about 1.8 × and 88%, respectively. The results suggest that STT-MRAM technology can be a solid alternative for energy-efficient cryogenic memory applications. </p>

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“…MOS technology operating at cryogenic temperatures provides some benefits, such as steeper subthreshold slope, increased carrier mobility, and increased saturation velocity, leading to semiconductor-based circuits with faster operation, reduced leakage, and improved energy-efficiency [4,5]. As shown in Figure 1, MOS technologies operating at cryogenic temperatures are interesting for a wide spectrum of applications including high-performance computing [6,7], control systems for quantum processors [8,9], and aerospace applications [5,10,11]. The need for electronic devices capable of operating at cryogenic temperatures has always been a sought-after feature in deep space applications; however, high-performance computing and especially quantum computing are now increasing the demand for processors and memories that can operate at very low temperatures.…”

Section: Introductionmentioning

confidence: 99%

“…The benefits of cooling down processors and memory systems to cryogenic temperatures as low as 77 K have recently been demonstrated [2,13,14]. The studies reported in [11,13,15] mainly focus on traditional embedded memories based on six-transistor static random access memory (6T-SRAM), which are shown to provide significant improvements in terms of performance. However, the relatively large bitcell area of 6T-SRAM limits the overall on-chip memory density and the many leakage paths present in these memories limit the achievable power savings [16].…”

Section: Introductionmentioning

confidence: 99%

Embedded Memories for Cryogenic Applications

2021

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The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

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A pFET-access radiation-hardened SRAM for extreme environments

Cited by 11 publications

References 5 publications

Design A Synchronous Single-Port Sram 1024x32xMUX4 Using 28NM Technology

Design A Synchronous Single-Port Sram 1024x32xMUX4 Using 28NM Technology

STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications

Embedded Memories for Cryogenic Applications

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