A PFM-Based Digital Pixel With an Off-Pixel Residue Measurement for Small Pitch FPAs

Abbasi, Shahbaz; Galioğlu, Arman; Shafique, Atia; Ceylan, Omer; Yazıcı, Melik; Gürbüz, Yaşar

doi:10.1109/tcsii.2016.2614339

Cited by 9 publications

(3 citation statements)

References 9 publications

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“…In previous designs [5,11] , a folding integration circuit has been widely adopted to reduce the value of the integration capacitance. However, owing to the residual charge of folding integration, the linearity of the circuit is considerably limited.…”

Section: Two-stage Quantization Architecturementioning

confidence: 99%

“…Analog-to-digital converters (ADCs) have been integrated with IRFPAs owing to their high noise performance with a short analog chain and low systemlevel hardware costs [2][3][4] . There is an increasing need for high-performance digital readout integrated circuits with small pixel pitch for Long-wave infrared (LWIR) Focal plane arrays (FPAs) [5] .…”

Section: Introductionmentioning

confidence: 99%

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A 16‐bit Hybrid ADC with Circular‐Adder‐Based Counting for 15μm Pitch 640×512 LWIR FPAs

Huang

Zhu

et al. 2020

Chin. j. electron.

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Section: Two-stage Quantization Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 16‐bit Hybrid ADC with Circular‐Adder‐Based Counting for 15μm Pitch 640×512 LWIR FPAs

Huang

Zhu

et al. 2020

Chin. j. electron.

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“…However, due to the integration structure, area inevitably becomes strained. Moreover, in order to achieve multi-self-reset operations, there has to be a complex feedback logic circuit [7][8][9]. Hence, it is difficult to achieve the multi-mode compatibility in a limited area based on the PFM method.…”

Section: Introductionmentioning

confidence: 99%

Design of a multi‐mode digital pixel with conversion data protection

Kong

Chang

2022

IET Circuits, Devices & Syst

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With the development of semiconductor technology, digital pixel has received widespread attention and is applied to various electronic products. However, due to the limitation of area, it forms a challenging task to design a digital pixel with multiple modes. In this paper, a pulse width modulation based digital pixel is proposed, which is compatible with five different modes. By using the multi-purpose capacitors and static random access memory structure, it can realise multi-mode conversion in an equivalent area to that of the single mode digital pixel without performance degradation. Furthermore, a corresponding logic control method is developed, such that the integrity of the frame data is ensured during mode conversion. The simulation result of our proposed digital pixel in Tower Jazz 0.18 μm process shows that in the bright field it achieves a dynamic range of 67 dB. In the dark field, it achieves a conversion gain up to 13.91 μV/e−, with input noise of 37.89 e−per pixel after correlated double sampling.

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A Novel Approach to Noise Shaping in Digital Pixels for Infrared Imagers using Over-Integration

Abbasi

Shafique

Ceylan

et al. 2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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Digital readout integrated circuits (DROICs) for small pitch infrared focal plane arrays (IR-FPAs) suffer from low in-pixel resolution owing to the limited pixel real estate. To this end, a new technique to improve the resolution of pulse frequency modulation (PFM) based pixels, using quantization charge noise shaping, is presented. Multiple integration operations are performed in a single frame and the quantization error from each integration phase is retained and effectively induced into the next integration phase. The result is a high pass noise transfer function (NTF) equivalent to what is obtained in a first order sigma delta modulator. Along with a theoretical analysis of the technique, a prototype based on a single pixel and a 2 nd order decimation filter is developed to demonstrate the performance of the proposed technique. With an in-pixel circuitry generating 5 bits, a resolution of 11 bits (65 dB) is achieved with an over-integration ratio of 64. With a 100 Hz frame rate and 64 integration operations per frame, a readout noise of 1100e-is measured at full-well fill from the test pixel fabricated in a 90nm CMOS process.

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A PFM-Based Digital Pixel With an Off-Pixel Residue Measurement for Small Pitch FPAs

Cited by 9 publications

References 9 publications

A 16‐bit Hybrid ADC with Circular‐Adder‐Based Counting for 15μm Pitch 640×512 LWIR FPAs

A 16‐bit Hybrid ADC with Circular‐Adder‐Based Counting for 15μm Pitch 640×512 LWIR FPAs

Design of a multi‐mode digital pixel with conversion data protection

A Novel Approach to Noise Shaping in Digital Pixels for Infrared Imagers using Over-Integration

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