A phase-change memory model for neuromorphic computing

Nandakumar, S. R.; Gallo, Manuel Le; Boybat, Irem; Rajendran, Bipin; Sebastian, Abu; Eleftheriou, Evangelos

doi:10.1063/1.5042408

Cited by 133 publications

(92 citation statements)

References 41 publications

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“…It is followed by pulses of gradually increasing voltage pulses (SET pulses) to then increase the conductance. Conductance response characteristic of PCM synapse we simulated, based on model developed in Nandakumar et al [48] (See Supplementary Material-Section 3 for more details), is more linear than RRAM i.e. programming current pulse of fixed magnitude 90 µA and duration 50 ns increase the conductance of the PCM synapse fairly linearly for a larger number of pulses ( ≈ 12) ( Fig.…”

Section: Device Level Comparisonmentioning

confidence: 99%

Comparing domain wall synapse with other non volatile memory devices for on-chip learning in analog hardware neural network

et al. 2020

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Resistive Random Access Memory (RRAM) and Phase Change Memory (PCM) devices have been popularly used as synapses in crossbar array based analog Neural Network (NN) circuit to achieve more energy and time efficient data classification compared to conventional computers. Here we demonstrate the advantages of recently proposed spin orbit torque driven Domain Wall (DW) device as synapse compared to the RRAM and PCM devices with respect to on-chip learning (training in hardware) in such NN. Synaptic characteristic of DW synapse, obtained by us from micromagnetic modeling, turns out to be much more linear and symmetric (between positive and negative update) than that of RRAM and PCM synapse. This makes design of peripheral analog circuits for on-chip learning much easier in DW synapse based NN compared to that for RRAM and PCM synapses. We next incorporate the DW synapse as a Verilog-A model in the crossbar array based NN circuit we design on SPICE circuit simulator. Successful on-chip learning is demonstrated through SPICE simulations on the popular Fisher's Iris dataset. Time and energy required for learning turn out to be orders of magnitude lower for DW synapse based NN circuit compared to that for RRAM and PCM synapse based NN circuits.

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Section: Device Level Comparisonmentioning

confidence: 99%

Comparing domain wall synapse with other non volatile memory devices for on-chip learning in analog hardware neural network

et al. 2020

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“…A common technique is to arrange such devices in a structure, called crossbar array, in which every device (or a pair of devices) is used to represent a single synaptic weight or, more generally, an entry in a matrix 5 . Memristive devices, such as phase-change memories (PCMs) 6 , 7 or resistive random-access memories (RRAMs) 8 , 9 , have been considered as candidates for such tasks. Although here we focus on ex situ training, such systems have been successfully utilised for in situ training too 10 , 11 .…”

Section: Introductionmentioning

confidence: 99%

Committee machines—a universal method to deal with non-idealities in memristor-based neural networks

et al. 2020

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Artificial neural networks are notoriously power- and time-consuming when implemented on conventional von Neumann computing systems. Consequently, recent years have seen an emergence of research in machine learning hardware that strives to bring memory and computing closer together. A popular approach is to realise artificial neural networks in hardware by implementing their synaptic weights using memristive devices. However, various device- and system-level non-idealities usually prevent these physical implementations from achieving high inference accuracy. We suggest applying a well-known concept in computer science—committee machines—in the context of memristor-based neural networks. Using simulations and experimental data from three different types of memristive devices, we show that committee machines employing ensemble averaging can successfully increase inference accuracy in physically implemented neural networks that suffer from faulty devices, device-to-device variability, random telegraph noise and line resistance. Importantly, we demonstrate that the accuracy can be improved even without increasing the total number of memristors.

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“…The mean of the conductance change per subsequent programming pulse decreases and its standard deviation increases causing a non-linear update behavior. We analyzed the state-dependent nature of the conductance change in the devices and developed a statistical model capturing the stochastic conductance evolution behavior 45 . The model response is also shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

“…Our PCM model incorporates this conductance drift and read noise (Supplementary Note 1). The drift in PCM is observed to re-initiate after each programming event 39,45 . To ensure that the model captures the drift re-initialization in PCM properly, we performed an experiment where the devices are applied with SET pulse sequences with different time delays.…”

Section: Resultsmentioning

confidence: 99%

Experimental Demonstration of Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses

Nandakumar

Boybat

Gallo

et al. 2020

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Spiking neural networks (Snn) are computational models inspired by the brain's ability to naturally encode and process information in the time domain. the added temporal dimension is believed to render them more computationally efficient than the conventional artificial neural networks, though their full computational capabilities are yet to be explored. Recently, in-memory computing architectures based on non-volatile memory crossbar arrays have shown great promise to implement parallel computations in artificial and spiking neural networks. In this work, we evaluate the feasibility to realize high-performance event-driven in-situ supervised learning systems using nanoscale and stochastic analog memory synapses. For the first time, the potential of analog memory synapses to generate precisely timed spikes in Snns is experimentally demonstrated. the experiment targets applications which directly integrates spike encoded signals generated from bio-mimetic sensors with in-memory computing based learning systems to generate precisely timed control signal spikes for neuromorphic actuators. More than 170,000 phase-change memory (PCM) based synapses from our prototype chip were trained based on an event-driven learning rule, to generate spike patterns with more than 85% of the spikes within a 25 ms tolerance interval in a 1250 ms long spike pattern. We observe that the accuracy is mainly limited by the imprecision related to device programming and temporal drift of conductance values. We show that an array level scaling scheme can significantly improve the retention of the trained Snn states in the presence of conductance drift in the pcM. combining the computational potential of supervised Snns with the parallel compute power of inmemory computing, this work paves the way for next-generation of efficient brain-inspired systems.

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A phase-change memory model for neuromorphic computing

Cited by 133 publications

References 41 publications

Comparing domain wall synapse with other non volatile memory devices for on-chip learning in analog hardware neural network

Comparing domain wall synapse with other non volatile memory devices for on-chip learning in analog hardware neural network

Committee machines—a universal method to deal with non-idealities in memristor-based neural networks

Experimental Demonstration of Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses

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