A Physical Explanation of Threshold Voltage Drift of SiC MOSFET Induced by Gate Switching

Jiang, Huaping; Qi, Xiaowei; Qiu, Guanqun; Zhong, Xiaohan; Tang, Lei; Mao, Hua; Wu, Zebing; Chen, Honggang; Li, Ran

doi:10.1109/tpel.2022.3161678

Cited by 31 publications

(9 citation statements)

References 16 publications

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“…This would help in keeping parameter variations due to GSI under control and within acceptable limits. We will discuss our model in detail later in this paper and explain how it fits the recent experimental observations of various groups [4][5][6][7].…”

Section: Introductionmentioning

confidence: 70%

“…While similar observations in silicon devices have been assigned to gate-sided hydrogen release [13], any model for GSI in SiC devices needs to consistently explain the main experimental observations reported by several independent groups [4][5][6][7]. These observations are:…”

Section: A Proposal For a Microscopic Model For Gsimentioning

confidence: 83%

“…For fast switching operation, a wide and flexible gate drive operation window is required including margins for overand undershoots and negative gate turn-off voltages to allow save turn-off. Within their lifetime, SiC MOSFETs are exposed to a large number of bipolar gate-switching events that can lead to systematic degradation of electrical parameters such as the threshold voltage and the on-resistance due to gate switching instability (GSI) [1][2][3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

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Assessing, Controlling and Understanding Parameter Variations of SiC Power MOSFETs in Switching Operation

Aichinger

Feil

Salmen

2023

KEM

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Semiconductor manufacturers and researchers have recently revealed that under specific bipolar gate switching conditions SiC MOSFETs exhibit parameter drift dynamics different from those typically observed in static qualification stress tests. In response to this finding, we present an approach for assessing the worst-case drift of data-sheet-relevant electrical parameters in a simple and transparent manner for a large variety of application profiles. We also introduce an empirical model that may explain the drift dynamics observed under gate switching stress; and discuss a recently developed interface characterization technique that has the potential to reveal the nature of point defects at the SiC/SiO2 interface presumably related to the gate switching instability in SiC MOSFETs.

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Section: Introductionmentioning

confidence: 70%

Section: A Proposal For a Microscopic Model For Gsimentioning

confidence: 83%

Section: Introductionmentioning

confidence: 99%

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Assessing, Controlling and Understanding Parameter Variations of SiC Power MOSFETs in Switching Operation

Aichinger

Feil

Salmen

2023

KEM

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“…7-9 in Part I, we know from basic CP theory [26] that A must have energy levels reaching down to the valence band E v , which we assume to be of type +/0, since SiC MOSFETs have a significant amount of such donor-like defects causing hysteresis [27], [28], [29], [30] and stretch out in C-V measurements [12]. However, since GSI depends on both V H and V L and also because a fall time dependence has been observed in other devices [9], we assume the defect to be amphoteric in the most general case, with an additional 0/− energy level somewhere close to E c , see Figs. 3 and 4.…”

Section: B "Source" Defect Site Amentioning

confidence: 98%

“…So far, the GSI phenomenon is poorly understood, and there is no accurate model available, which allows for a deeper understanding. While some models have been previously proposed, these were based on some form of local electric-field enhancement and subsequently increased charge trapping [9], [10]. However, as discussed in Part I, GSI does not result in the creation of fixed charges but predominantly creates active defects close to the conduction band of SiC [11], [12].…”

mentioning

confidence: 99%

Gate Switching Instability in Silicon Carbide MOSFETs—Part II: Modeling

Grasser,

Feil,

Waschneck

et al. 2024

IEEE Trans. Electron Devices

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It has recently been observed that bipolar switching between accumulation and inversion can result in an unexpected threshold voltage drift in SiC MOSFETs. This phenomenon has been termed gate switching instability (GSI) and is characterized by power-law time exponents close to unity, significantly larger than what is typically observed for ordinary bias temperature instability (BTI) during static or unipolar switching stress. Since the bias, frequency, and temperature dependence of GSI are the same as what is seen in charge pumping (CP) experiments, we stipulate that recombination events at the interface lead to recombination-enhanced defect reactions (REDRs), which can eventually lead to degradation. Based on these observations, we develop a comprehensive physical model for GSI, discuss its features, derive a closed form analytical solution, and finally validate the model against detailed experimental data.

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A novel SiC VD-MOSFET with optimized P-type shielding structure in JFET region for improved short circuit robustness

Guo,

Zhai,

et al. 2024

Eng. Res. Express

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This paper investigates the short-circuit characteristics of Silicon Carbide (SiC) VerticalDouble-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (VD-MOSFET) utilizing TCAD tools. Expanding upon the conventional VD-MOSFET framework, a novel900V SiC VD-MOSFET with two P-type shielding layer introduced in JFET region, PW-MOSFET, is proposed and designed. In contrast to the traditional VD MOSFET, PW- -MOSFET not only significantly improves short-circuit (SC) reliability but also optimizes static performance. Simulation results reveal that PW-MOSFET demonstrates notably superior SC performance at a DC link voltage of 600V compared to the traditional VD-MOSFET, with a 63% increase in Short-Circuit Withstand Time (SCWT) and a 25% enhancement in Baliga Figure of Merit (FOM). The key factor contributing to this performance enhancement is attributed to the advantageous role of the P-type shielding layer, facilitating adjustments in the current flow path, thereby suppressing saturation current and enhancing the reliability of short-circuit events. Furthermore, the issue of increased characteristic on-state resistance (Ron, sp) resulting from the introduction of the P-type shielding layer is addressed by augmenting the doping concentration in the JFET region.

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A Physical Explanation of Threshold Voltage Drift of SiC MOSFET Induced by Gate Switching

Cited by 31 publications

References 16 publications

Assessing, Controlling and Understanding Parameter Variations of SiC Power MOSFETs in Switching Operation

Assessing, Controlling and Understanding Parameter Variations of SiC Power MOSFETs in Switching Operation

Gate Switching Instability in Silicon Carbide MOSFETs—Part II: Modeling

A novel SiC VD-MOSFET with optimized P-type shielding structure in JFET region for improved short circuit robustness

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