A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors

Abstract

This work studies physical-level characteristics of the recently proposed compacted matrix instruction scheduler for dynamically-scheduled, superscalar processors. Previous work focused on the matrix scheduler's architecture and argued in support of its speed and scalability advantages. However, no physical-level implementation or models were reported for it. Using full-custom layouts in a commercial 90 nm fabrication technology, this work investigates the latency and energy variations of the compacted matrix and its accompanying logic as a function of the issue width, the window size, and the number of global recovery checkpoints. This work also proposes an energy optimization that throttles unnecessary pre-charges and evaluations. This optimization reduces energy by 10% and 18% depending on the scheduler size.

LaZy superscalar

“…al. [25]'s work on the physical characteristics of a matrix scheduler. LaZy appears to consume more power when performance increase is high, with mcf and sjeng being exceptions.…”

“…al. [25]. It shows the power usage on a matrix read or write based on the number of rows in the matrix as well as the delay of the matrix circuit.…”