A Physics-Based Modeling of Interelectrode MOS Capacitances of Power MOSFET and IGBT

Raël, Stéphane; Davat, Bernard

doi:10.1109/tpel.2008.2002092

Cited by 13 publications

(5 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Outra relevante discussão refere-se aos disparos inadvertidos que podem ser causados pelo efeito Miller, quando um dispositivo é submetido à variação positiva de sua tensão coletor-emissor. De acordo com [33], durante o regime de alta inversão da capacitância porta-coletor (tensão negativa de porta) ocorre, praticamente, o completo desaparecimento do acoplamento capacitivo entre a porta e o coletor. Essa característica não é compartilhada, por exemplo, pelos exemplo, pelos exem IGBTs de média tensão que necessitam dos circuitos de proteção chamados "active Miller clamp".…”

Section: Solução De Disparounclassified

Solução Integrada para o Disparo de IGBTs Conectados em Série Baseada no Comando Típico de Tiristores

Fortes¹,

Mendes²,

Cortizo³

2019

Eletrônica de Potência

View full text Add to dashboard Cite

dentro do mercado de inversores de média tensão (até 4,16kV) kV) kV e menor potência (até 1MW) MW) MW , utilizando essa tecnologia. Esse fato está relacionado com a dificuldade de garantir o compartilhamento dinâmico e estático de tensão entre IGBTs, originando circuitos de disparo complexos e com custo relativo elevado, se comparado com os componentes que esses pretendem comandar. Dessa forma, o presente artigo visa apresentar uma alternativa simples e de baixo custo, entretanto, efetiva para o disparo de IGBTs de baixa tensão associados em série, especificamente para o modelo de encapsulamento TO-247. 247. 247 São apresentados resultados experimentais mostrando os comportamentos da solução em várias condições operacionais.

show abstract

Section: Solução De Disparounclassified

Solução Integrada para o Disparo de IGBTs Conectados em Série Baseada no Comando Típico de Tiristores

Fortes¹,

Mendes²,

Cortizo³

2019

Eletrônica de Potência

View full text Add to dashboard Cite

show abstract

“…1. This model only includes the MOSFET turn-on dynamic characteristic modeling, parasitic capacitance, lead and bonding wire parasitic impedance, and V GS and V BS amplifying effect (g m and g mBS ) [17]. For analysis and simulation consideration, a simplified model is shown in Fig.…”

Section: Mosfet and Circuit System Modelingmentioning

confidence: 99%

Sensing Power MOSFET Junction Temperature Using Circuit Output Current Ringing Decay

Niu

Lorenz

2015

IEEE Trans. on Ind. Applicat.

View full text Add to dashboard Cite

Junction temperature (T j ) sensing requirements for fast MOSFET junction temperature control and high-power fast switching power converter protection are not easily met with nonintrusive techniques. This paper presents a noninvasive circuitmodel-based sensing method suitable for a high-bandwidth hard-switching converter power MOSFET junction temperature estimation without any additional temperature detector. For the purpose of demonstrating MOSFET junction temperature sensing, a chopper circuit is used. The ringing superimposed with a circuit load current is used for MOSFET junction temperature estimation. A "gate drive-R DS−on −L−C" resonant model is implemented, indicating the mechanism of power MOSFET turn-on dynamics. Modeling includes the gate-drive output parasitics, power MOSFET intrinsic parameters, PCB parasitics, and load parasitics. To evaluate the methodology, LTspice simulation and experimental results are studied.

show abstract

“…Although the IGBT is superior to traditional power devices, the latch-up phenomenon arises which occurs due to the inherent thyristor structure [22]. Also shown are the locations of capacitive couplings for the reverse transfer capacitance, C res , within the IGBT [23].…”

Section: A Device Structurementioning

confidence: 99%

Turn-Off Time as an Early Indicator of Insulated Gate Bipolar Transistor Latch-up

Brown

Abbas

Ginart

et al. 2012

IEEE Trans. Power Electron.

114

View full text Add to dashboard Cite

In this paper, effects preceding a latch-up fault in insulated gate bipolar transistors (IGBTs) are studied. Primary failure modes associated with IGBT latch-up faults are reviewed. Precursors to latch-up, primarily an increase in turn-off time as a consequence of elevated junction temperature, are examined for an IGBT. The relationship between junction temperature and turn-off time is explained by modeling the parasitic properties of an IGBT. A metric is derived from the model to standardize the relative estimates in junction temperature from measurements of turn-off time. To evaluate the effects preceding latch-up in-situ, seeded fault testing is conducted on a three-phase power inverter using aged transistors induced with a fault located in the die-attach solder layer. Experimental results demonstrated the feasibility of using the proposed metric as a precursor to transistor latch-up.

show abstract

A Physics-Based Modeling of Interelectrode MOS Capacitances of Power MOSFET and IGBT

Cited by 13 publications

References 16 publications

Solução Integrada para o Disparo de IGBTs Conectados em Série Baseada no Comando Típico de Tiristores

Solução Integrada para o Disparo de IGBTs Conectados em Série Baseada no Comando Típico de Tiristores

Sensing Power MOSFET Junction Temperature Using Circuit Output Current Ringing Decay

Turn-Off Time as an Early Indicator of Insulated Gate Bipolar Transistor Latch-up

Contact Info

Product

Resources

About