A Picosecond-Resolution Digitally-Controlled Timing Generator With One-Clock-Latency at Arbitrary Instantaneous Input

Park, Jaehan; Ahn, Cheolmin; Hong, Jaehyeong; Sim, Jae‐Yoon

doi:10.1109/tcsii.2020.3010535

Cited by 2 publications

(1 citation statement)

References 14 publications

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“…Table I summarizes the performance of the DPC and compares it with that of prior art. The power consumption is higher in comparison with [5], [6] and [18] mainly due to the operating frequency and the number of the output phases. In terms of linearity, although the DPC's may not demonstrate favorable INL, the achieved DNL is within the fine range.…”

Section: Resultsmentioning

confidence: 99%

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

Khanghah¹,

Sadeghipour²,

Kelly³

et al. 2022

IEEE Trans. Circuits Syst. I

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This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC's resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. Index Terms-Digital to phase converter (DPC), clock and data recovery (CDR), phase interpolator (PI), wireline and optical communication.

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Section: Resultsmentioning

confidence: 99%

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

Khanghah¹,

Sadeghipour²,

Kelly³

et al. 2022

IEEE Trans. Circuits Syst. I

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A multi-functional arbitrary timing generator based on a digital-to-time converter

Kong,

Fu,

Liu

et al. 2023

Review of Scientific Instruments

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This paper proposes a new high-resolution digital-to-time converter architecture based on a field programmable gate array and digital-to-analog converter (DAC). A real-time algorithm of time–-amplitude mapping is proposed, which converts the vertical resolution of the DAC to the timing resolution and realizes the ultra-high resolution timing signal generation. Moreover, the relationship between the timing resolution and the vertical resolution and the sampling rate of DAC is discussed. Based on this, arbitrarily distributed random timing signals and editable timing signal sequence functions are realized. This method is verified in the experiment on Xilinx XCKU040 and Texas Instrument DAC37J82. Furthermore, a timing resolution of 1 ps is realized. A time range of 4.2 ns to 999 s, an editable sequence length of 1–128k, and excellent nonlinear performance are achieved. In addition, functions for arbitrarily distributed random timing signals and signal bursts are tested. This method can be flexibly deployed on existing hardware and satisfy almost all test requirements.

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A Picosecond-Resolution Digitally-Controlled Timing Generator With One-Clock-Latency at Arbitrary Instantaneous Input

Cited by 2 publications

References 14 publications

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

A multi-functional arbitrary timing generator based on a digital-to-time converter

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