A pipeline architecture for traffic sign classification on an FPGA

Zhou, Yuteng; Chen, Zhilu; Huang, Xinming

doi:10.1109/iscas.2015.7168792

Cited by 12 publications

(13 citation statements)

References 10 publications

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“…To avoid the expensive floating point computation of arctangents, this study refers to the scheme of Kadota et al [ 16 ] and Zhou et al [ 27 ], which uses a compared method to obtain corresponding bins. Firstly, the study utilizes Algorithm 1 to determine θ ( i , j )’s rough range.…”

Section: Proposed Hardware Implementationmentioning

confidence: 99%

Pure FPGA Implementation of an HOG Based Real-Time Pedestrian Detection System

Luo

2018

Sensors

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In this study, we propose a real-time pedestrian detection system using a FPGA with a digital image sensor. Comparing with some prior works, the proposed implementation realizes both the histogram of oriented gradients (HOG) and the trained support vector machine (SVM) classification on a FPGA. Moreover, the implementation does not use any external memory or processors to assist the implementation. Although the implementation implements both the HOG algorithm and the SVM classification in hardware without using any external memory modules and processors, the proposed implementation’s resource utilization of the FPGA is lower than most of the prior art. The main reasons resulting in the lower resource usage are: (1) simplification in the Getting Bin sub-module; (2) distributed writing and two shift registers in the Cell Histogram Generation sub-module; (3) reuse of each sum of the cell histogram in the Block Histogram Normalization sub-module; and (4) regarding a window of the SVM classification as 105 blocks of the SVM classification. Moreover, compared to Dalal and Triggs’s pure software HOG implementation, the proposed implementation‘s average detection rate is just about 4.05% less, but can achieve a much higher frame rate.

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Section: Proposed Hardware Implementationmentioning

confidence: 99%

Pure FPGA Implementation of an HOG Based Real-Time Pedestrian Detection System

Luo

2018

Sensors

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“…However, no single feature-classifier pair has been reported in literature which is better discriminant as well as computationally less complex than HOG as noted by Dollar et al [8], Rodrigo et al [15], Achmad et al [42] and Yong et al [37]. Hence, in the recent years many dedicated hardware designs for object detection have adopted HOG-Linear SVM despite its computational complexity [53][54][55][56][57][58][59][60]. To this end, in the next section we propose a low complexity pedestrian detection framework which is well suited for small embedded systems without GPU/SSE support and requires minimal hardware resources when implemented on an FPGA.…”

Section: Real-time Performance Of Pedestrian Detectorsmentioning

confidence: 99%

A Low-Complexity Pedestrian Detection Framework for Smart Video Surveillance Systems

Bilal

Khan

et al. 2017

IEEE Trans. Circuits Syst. Video Technol.

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Pedestrian detection is a key problem in computer vision and is currently addressed with increasingly complex solutions involving compute-intensive features and classification schemes. In this scope, Histogram of Oriented Gradients (HOG) in conjunction with linear SVM classifier is considered to be the single most discriminative feature which has been adopted as a stand-alone detector as well as a key instrument in advance systems involving hybrid features and cascaded detectors. In this paper, we propose a pedestrian detection framework which is computationally less expensive as well as more accurate than HOG-linear SVM. The proposed scheme exploits the discriminating power of the locally significant gradients in building orientation histograms without involving complex floating point operations while computing the feature. The integeronly feature allows the use of powerful Histogram Intersection Kernel SVM classifier in a fast look-up table based implementation. Resultantly, the proposed framework achieves at least 3% more accurate detection results than HOG on standard datasets while being 1.8 and 2.6 times faster on conventional desktop PC and embedded ARM platforms respectively for a single scale pedestrian detection on VGA resolution video. Additionally, hardware implementation on Altera Cyclone IV FPGA results in more than 40% savings in logic resources compared to its HOG-Linear SVM competitor. Hence, the proposed feature and classification setup is shown to be a better candidate as the single most discriminative pedestrian detector than currently accepted HOG-linear SVM.

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“…In particular, the authors in [8] propose a CPU-FPGA implementation for High-Performance Face Detection with conventional images; they utilize an Altera Stratix-V A7 FPGA (∼55% Logic Elements and ∼50% M20K RAM) to achieve 30x speedup compared to an Intel Core i5-4590 CPU. In [9], they develop a pipelined architecture for traffic sign classification; it processes 241.7 Megapixel/sec (3channel pixels, RGB) at 241.7 MHz by utilizing 8.2K LUTs and 11.8K DFFs on a Xilinx Zynq ZC706, whereas it achieves 106x speedup vs SW execution on Intel Core i5 CPU.…”

Section: Related Workmentioning

confidence: 99%

FPGA acceleration of hyperspectral image processing for high-speed detection applications

Vellas¹,

Lentaris²,

Maragos³

et al. 2017

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

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Recent advances in photonics and imaging technology allow the development of cutting-edge, lightweight hyperspectral sensors, both push-broom/line-scanning and snapshot/frame. At the same time, emerging applications in robotics, food inspection, medicine and earth observation are posing critical challenges on real-time processing and computational efficiency, both in terms of accuracy and power consumption. In this direction, in the current paper, we accelerate hyperspectral processing kernels by utilizing FPGAs, i.e., Zynq-7000 SoC, to perform similaritybased matching of spectral signatures. We propose a custom HW architecture based on multi-level parallelization, modularity, and parametric VHDL coding, which allows for in-depth design space exploration and trade-off analysis. Depending on configuration, our implementation processes 22−107 Megapixels per second providing an acceleration of 40−355x vs Intel-i3 CPU and 360−10 4 x vs the embedded ARM Cortex A9, whereas the overall detection quality ranges from 56% to 97% when evaluated with multiple objects and images of 285 spectral channels.

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A pipeline architecture for traffic sign classification on an FPGA

Cited by 12 publications

References 10 publications

Pure FPGA Implementation of an HOG Based Real-Time Pedestrian Detection System

Pure FPGA Implementation of an HOG Based Real-Time Pedestrian Detection System

A Low-Complexity Pedestrian Detection Framework for Smart Video Surveillance Systems

FPGA acceleration of hyperspectral image processing for high-speed detection applications

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